oaverilogcallbacksout.cpp

openaccess与verilog互相转化时所用的源代码

    if (dest.getType() == oacBundleNameType) {
	oaBundleName	*destBundle = dest.getBundle();

	if (src.getType() == oacBundleNameType) {
	    const oaBundleName	*srcBundle = src.getBundle();

	    for (oaUInt4 i = 0; i < srcBundle->getNumMembers(); i++) {
		destBundle->append((*srcBundle)[i]);
	    }
	} else {
	    switch (src.getType()) {
	      case oacScalarNameType:
		destBundle->append(*src.getScalar());
		break;

	      case oacVectorNameType:
		destBundle->append(*src.getVector());
		break;

	      case oacVectorBitNameType:
		destBundle->append(*src.getVectorBit());
		break;
	    }
	}
    } else {
	oaBundleName	bundle;

	switch (dest.getType()) {
	  case oacScalarNameType:
	    bundle.append(*dest.getScalar());
	    break;

	  case oacVectorNameType:
	    bundle.append(*dest.getVector());
	    break;

	  case oacVectorBitNameType:
	    bundle.append(*dest.getVectorBit());
	    break;
	}

	switch (src.getType()) {
	  case oacScalarNameType:
	    bundle.append(*src.getScalar());
	    break;

	  case oacVectorNameType:
	    bundle.append(*src.getVector());
	    break;

	  case oacVectorBitNameType:
	    bundle.append(*src.getVectorBit());
	    break;
	}

	dest = bundle;
    }
}



// *****************************************************************************
// CallbacksOut::binEquivNets()
//
// This function sorts the given net and the equivalent nets of the given net 
// into bins of inputs and outputs.  This function uses the isInput function to
// determine if a given net is an input or an output.  Nets that are not inputs
// are assumed to be outputs.
// *****************************************************************************
void
CallbacksOut::binEquivNets(oaModBitNet		    *net,
			   std::set<oaModBitNet*>   &inputs,
			   std::set<oaModBitNet*>   &outputs) const
{
    if (isInput(net)) {
	inputs.insert(net);
    } else {
	outputs.insert(net);
    }

    oaIter<oaModBitNet>	netIter(net->getEquivalentNets());

    while (oaModBitNet *equiv = netIter.getNext()) {
	if (isInput(equiv)) {
	    inputs.insert(equiv);
	} else {
	    outputs.insert(equiv);
	}
    }
}



// *****************************************************************************
// CallbacksOut::combineBitWithBit()
//
// If the base name of the source is equal to the base name of destination then
// this function the combines the source bit name with the destination bit name.
// To combine the bit names, a vector name is formed using the base name of the
// destination.  The index of the destination becomes the start value of the
// vector and the index of the source becomes the stop value of the vector.
// If the base names are not equal then the destination becomes a bundle 
// where the first member is the original destination and the second member
// is the source.
// *****************************************************************************
void  
CallbacksOut::combineBitWithBit(const oaVectorBitName	*src,
				oaName			&dest)
{
    oaVectorBitName *destBit = dest.getVectorBit();
    oaScalarName    destBase;
    oaScalarName    srcBase;

    destBit->getBaseName(destBase);
    src->getBaseName(srcBase);

    if (verNS.isEqual(destBase, srcBase)
	&& (src->getIndex() == destBit->getIndex() + 1 
	    || src->getIndex() + 1 == destBit->getIndex())) {
	dest = oaVectorName(destBase, destBit->getIndex(), src->getIndex());
    } else {
	addToBundle(*src, dest);
    }
}



// *****************************************************************************
// CallbacksOut::combineBitWithVector()
//
// If the base name of the source is equal to the base name of destination then
// this function the combines the source bit name with the destination vector
// name by replacing the stop value of the destination with bit's index. If the
// base names are not equal or if the source bit's index is not an increment or 
// decrement of the end of the destination range, then the destination becomes a
// bundle where the first member is the original destination and the second 
// member is the source.
// *****************************************************************************
void   
CallbacksOut::combineBitWithVector(const oaVectorBitName    *src,
				   oaName		    &dest)
{
    oaVectorName    *destV = dest.getVector();
    oaScalarName    destBase;
    oaScalarName    srcBase;

    destV->getBaseName(destBase);
    src->getBaseName(srcBase);

    oaBitOrderEnum  destOrder;

    if (destV->getStart() > destV->getStop()) {
	destOrder = oacDescendingBitOrder;
    } else if (destV->getStart() < destV->getStop()) {
	destOrder = oacAscendingBitOrder;
    }

    if (verNS.isEqual(destBase, srcBase)) {
	if (destOrder == oacDescendingBitOrder
	    && src->getIndex() + 1 == destV->getStop()) {
	    destV->setStop(src->getIndex());
	} else if (destOrder == oacAscendingBitOrder 
		   && src->getIndex() == destV->getStop() + 1) {
	    destV->setStop(src->getIndex());
	} else {
	    addToBundle(*src, dest);
	}
    }  else {
	addToBundle(*src, dest);
    }
}



// *****************************************************************************
// CallbacksOut::isInput()
//
// This function returns true if the net has an input term.  If the net has
// an output term this function returns false.  If the net has no terms, then 
// this function returns true if the net has an input instTerm. Otherwise, this
// function returns false.
// *****************************************************************************
oaBoolean
CallbacksOut::isInput(oaModBitNet   *net) const
{
    oaBoolean		isOutput = false;
    oaIter<oaModTerm>	termIter(net->getTerms());

    while (oaModTerm *term = termIter.getNext()) {
	if (term->getTermType() == oacInputTermType) {
	    return true;
	} else if (term->getTermType() == oacOutputTermType) {
	    isOutput = true;
	}
    }

    if (isOutput) {
	return false;
    }

    oaIter<oaModInstTerm>   itermIter(net->getInstTerms());

    while (oaModInstTerm *iterm = itermIter.getNext()) {
	if (iterm->getTerm()
	    && iterm->getTerm()->getTermType() == oacInputTermType) {
	    
	    return true;
	}
    }

    return false;
}


// *****************************************************************************
// CallbacksOut::orderTerms()
//
// This function orders all terminals using the CmpTerms comparison functor.
// *****************************************************************************
void       
CallbacksOut::orderTerms(oaModule   &cell)
{
    oaIter<oaModTerm>	termIter(cell.getTerms(oacTermIterAll));
    
    terms.clear();

    while (oaModTerm *term = termIter.getNext()) {
	if (testProduceTerm(term)) {
	    terms.push_back(term);
	}
    }

    std::sort(terms.begin(), terms.end(), CmpTerms());

    oaUInt4	position = 0;

    oaScalarName    cn;
    cell.getName(cn);
    oaString	c;
    cn.get(c);

    for (TermIter iter = terms.begin(); iter != terms.end(); iter++) {
	termPosition->set((*iter), position++);
    }
}



// *****************************************************************************
// CallbacksOut::orderInstTerms()
//
// This function loads the list of InstTerms and sorts them with the 
// CmpInstTerms comparison functor.  This function is called when the instance
// is not bound.
// *****************************************************************************
void       
CallbacksOut::orderInstTerms(const oaModInst	&inst)
{
    iterms.clear();

    oaIter<oaModInstTerm>   itermIter(inst.getInstTerms(oacInstTermIterAll));
    
    while (oaModInstTerm *iterm = itermIter.getNext()) {
	if (testProduceInstTerm(iterm)) {
	    if (itermPrinted->get(iterm) == NotPrinted) {
		iterms.push_back(iterm);
		markInstTermPrinted(iterm);
	    }
	}
    }
    
    std::sort(iterms.begin(), iterms.end(), CmpInstTerms());
}



// *****************************************************************************
// CallbacksOut::markInstTermPrinted()
//
// This function marks the given InstTerm as printed so it will not be produced
// more than once.  If the InstTerm is an implicit InstTerm that contains
// explicit InstTerms (e.g. a multi-bit implicit InstTerm), then all the
// explicit members of the InstTerm are also marked as printed.  This function
// is called when the instance is not bound.
// *****************************************************************************
void       
CallbacksOut::markInstTermPrinted(oaModInstTerm	*iterm)
{
    itermPrinted->set(iterm, Printed);

    if (iterm->isImplicit()) {
	oaModInstTerm	*expl;
	oaName		itermN;

	if (!iterm->usesTermPosition()) {
	    iterm->getTermName(itermN);
	} else {
	    return;
	}

	oaString    itermNStr;

	for (oaUInt4 i = 0; i < itermN.getNumBits(); i++) {
	    itermN.getBitName(verNS, i, itermNStr);

	    oaName  explN(verNS, itermNStr);

	    expl = oaModInstTerm::find(iterm->getInst(), explN);

	    if (expl) {
		itermPrinted->set(expl, Printed);
	    }	
	}
    }
}


// *****************************************************************************
// CallbacksOut::busNameToDecl()
//
// This function constructs a string suitable for use in a net or port 
// declaration from the given vector name.  The range of the vector must appear
// before the base name.
// *****************************************************************************
void       
CallbacksOut::busNameToDecl(const oaVectorName	&name,
			    oaString		&decl) const
{
    oaString	baseName;
    
    name.getBaseName(verNS, baseName);
    decl.resize(128);
    decl.format("%s%u%s%u%s %s", (const char*) rangePrefix, name.getStart(), 
			         (const char*) rangeSep, name.getStop(), 
			         (const char*) rangeSuffix,
			         (const char*) baseName);
}



// *****************************************************************************
// CallbacksOut::numBits()
//
// This function calculates the number of bits in the input string that 
// that represents a binary number and returns the result as an oaString.
// *****************************************************************************
oaString       
CallbacksOut::numBits(const oaString	&binaryString) const
{
    return intToStr(binaryString.getLength());
}



// *****************************************************************************
// CallbacksOut::intToStr()
//
// This function returns an oaString that represents the given input unsigned
// integer.
// *****************************************************************************
oaString       
CallbacksOut::intToStr(oaUInt4	integer) const
{
    char    buf[64];
    
    sprintf(buf, "%u", integer);
    return buf;
}



// *****************************************************************************
// CallbacksOut::testProduceTerm()
//
// This function returns true if the given terminal should be produced, 
// otherwise it returns false.  If the preserve interface option is in effect,
// then the terminal will be produced only if it is an interface terminal.  If 
// the preserve interface option is not in effect, then the terminal will be
// produced only if the terminal is explicit.
// *****************************************************************************
oaBoolean     
CallbacksOut::testProduceTerm(const oaModTerm	*term) const
{
    return options.testPreserveInterface() ? term->isInterface()
					   : !term->isImplicit();
}



// *****************************************************************************
// CallbacksOut::testProduceInstTerm()
//
// This function returns true if the given InstTerm should be produced, 
// otherwise it returns false.  This function is called only when the instance
// is not bound.  No InstTerms can be bound in this case, so all explicit
// InstTerms that are connected to nets will be produced.
// *****************************************************************************
oaBoolean     
CallbacksOut::testProduceInstTerm(const oaModInstTerm	*iterm) const
{
    return !iterm->isImplicit() && iterm->getNet();
}



// *****************************************************************************
// CallbacksOut::isTieHigh()
//
// These functions returnstrue if connections to the given bitNet should be 
// treated as 1'b1 connections.
// *****************************************************************************
oaBoolean     
CallbacksOut::isTieHigh(const oaModBitNet   *net) const
{
    return net == tieHighNet;
}

oaBoolean     
CallbacksOut::isTieHigh(const oaString	&netExpr,
			const oaBoolean	isGlobal,
			const oaSigType	&sigType) const
{
    return  netExpr == tieHighNetStr;
}



// *****************************************************************************
// CallbacksOut::isTieLow()
//
// These functions return true if connections to the given bitNet should be 
// treated as 1'b0 connections.
// *****************************************************************************
oaBoolean     
CallbacksOut::isTieLow(const oaModBitNet    *net) const
{
    return net == tieLowNet;
}

oaBoolean     
CallbacksOut::isTieLow(const oaString	&netExpr,
		       const oaBoolean	isGlobal,
		       const oaSigType	&sigType) const
{
    return  netExpr == tieLowNetStr;
}



END_VERILOG_NAMESPACE