oaverilogcallbacksout.cpp

openaccess与verilog互相转化时所用的源代码

    write(");\n");
    decIndent();
}



// *****************************************************************************
// CallbacksOut::writeConnsByPosition()
//
// Given a list of connections, this function write the connections as a set
// of connections by position.
// *****************************************************************************
void
CallbacksOut::writeConnsByPosition(ConnectionList   &connList) 
{    
    oaUInt4	lastPosition = oacNullIndex;
    oaBoolean	first = true;

    for (ConnectionListIter iter = connList.begin(); iter != connList.end(); 
	 iter++) {

	if (first) {
	    write(" (\n");
	}

	if (!first) {
	    write(",\n");
	}

	for (oaUInt4 p = lastPosition; 
	     p != oacNullIndex && (*iter)->getPosition() != oacNullIndex 
	     && p < (*iter)->getPosition() - 1; p++) {

	    writeIndent(",\n");
	}

	writeHierConn((*iter)->getNet());
	
	first = false;
	lastPosition = (*iter)->getPosition();
    }

    if (first) {
	write(" (");
    }

    write(");\n");
    decIndent();
}



// *****************************************************************************
// CallbacksOut::writeHierConn()
//
// This function writes a hierarchical connection between a given port 
// identifier and a given net expression.
// *****************************************************************************
void       
CallbacksOut::writeHierConn(const oaString  &portID,
			    const oaString  &netExpr) const
{
    writeIndent("%s%s(%s)", (const char*) hierSep, (const char*) portID, 
	        (const char*) netExpr);
}



// *****************************************************************************
// CallbacksOut::writeHierConn()
//
// This function writes a hierarchical connection using positional syntax.
// *****************************************************************************
void       
CallbacksOut::writeHierConn(const oaString  &netExpr) const
{
    writeIndent("%s", (const char*) netExpr);
}



// *****************************************************************************
// CallbacksOut::getNextPortNet()
//
// This function builds the inst term and net name strings for the module
// instance connection at the given position.  The position of the iterator 
// will be advanced to next inst term in the container. This function returns 
// true as long as there are terminals to produce.  This function is used when
// the instance is not bound.
// *****************************************************************************
oaBoolean
CallbacksOut::getNextPortNet(InstTermIter   &itermIter,
			     Connection	    &connection)
{
    if (itermIter == iterms.end()) {
	return false;
    }

    return collectInstTerms(itermIter, connection);
}



// *****************************************************************************
// CallbacksOut::getNextPortNet()
//
// This function builds the term and net name strings for the terminal at the 
// given position in the terminal container.  The position of the iterator 
// will be advanced to next terminal in the container. Terminals that occupied 
// the same position in the original Verilog will re-grouped into a single 
// terminal.
// *****************************************************************************
oaBoolean    
CallbacksOut::getNextPortNet(TermIter	&termIter,
			     oaString	&portID,
			     oaString	&netExpr)
{
    if (termIter == terms.end()) {
	return false;
    }

    return collectTerms(termIter, portID, netExpr);
}



// *****************************************************************************
// CallbacksOut::writeEndModule()
//
// This function writes the endmodule statement.
// *****************************************************************************
void
CallbacksOut::writeEndModule(oaModule	&cell)
{
    oaScalarName    moduleName;
    oaString	    moduleNameStr;

    cell.getName(moduleName);
    moduleName.get(verNS, moduleNameStr);

    write("%s %s %s\n\n" , (const char*) endModuleKeyword, getCommentPrefix(),
	  (const char*) moduleNameStr);
}



// *****************************************************************************
// CallbacksOut::getBusNetDecl()
//
// This function produces a representation of the bus name suitable for a net
// declaration statement.  It returns false if the net name has already been
// produced otherwise it returns true.  This function will try to find a net
// that spans the full range of the given BusDef.  If such a net is found, then
// the name of that net is used.  If no nets match the full range, then a name
// is constructed using the name of the BusNetDef, the bit order of the def and
// the range of the def.  If the bit order on the BusNetDef is None then the
// bit order is assumed to be Ascending.
// *****************************************************************************
oaBoolean
CallbacksOut::getBusNetDecl(oaModBusNetDef  *def,
			    oaString	    &name)
{
    if (busNetPrinted->get(def) == Printed) {
	return false;
    }

    busNetPrinted->set(def, Printed);

    oaUInt4  start = def->getMaxIndex();
    oaUInt4  stop  = def->getMinIndex();
    
    // Try to find a net that represents the full range of the BusNetDef.
    oaScalarName    defName;
    def->getName(defName);

    oaModBusNet	*net = oaModBusNet::find(def->getModule(), defName, start, stop,
				         1);

    if (net) {
	oaVectorName	busName;
	
	net->getName(busName);
	busNameToDecl(busName, name);
	return true;
    }

    net = oaModBusNet::find(def->getModule(), defName, stop, start, 1);

    if (net) {
	oaVectorName	busName;
	
	net->getName(busName);
	busNameToDecl(busName, name);
	return true;
    }

    if (def->getBitOrder() == oacAscendingBitOrder) {
	oaUInt4	temp = start;
	start = stop;
	stop = temp;
    }

    busNameToDecl(oaVectorName(defName, start, stop), name);

    return true;
}



// *****************************************************************************
// CallbacksOut::getNetName()
//
// This function produces the name of the given net as a valid net expression 
// for IEEE 1364-2001 Verilog. If the net is a bus net and the net represents 
// the full range of the bus, the net name is taken from the name of the 
// busDef of the net.
// *****************************************************************************
void
CallbacksOut::getNetName(const oaModNet	*net,
			 oaName		&name)
{
    oaModBusNetDef  *busDef = NULL;

    switch (net->getType()) {
      case oacModBusNetType:
        busDef = ((oaModBusNet*) net)->getDef();
	break;

      case oacModBusNetBitType:
        busDef = ((oaModBusNetBit*) net)->getDef();
	break;
    }

    if (busDef && net->getNumBits() == busDef->getNumBits()) {
	oaScalarName    base;

	busDef->getName(base);
	name = base;
    } else {
	net->getName(name);
    }
}


// *****************************************************************************
// CallbacksOut::getInstTermName()
//
// This function produces the name of the given inst terminal as a valid port
// identifier for IEEE 1364-2001 Verilog.  This function is used when the 
// instance is not bound. 
// *****************************************************************************
oaBoolean
CallbacksOut::getInstTermName(const oaModInstTerm   *iterm,
			      oaString		    &portID)
{
    if (iterm->usesTermPosition()) {
	return false;
    }

    oaName  name;

    iterm->getTermName(name);

    switch (name.getType()) {
      case oacVectorNameType:
	name.getVector()->getBaseName(verNS, portID);
	break;

      case oacVectorBitNameType:
	name.getVectorBit()->getBaseName(verNS, portID);
	break;

      default:
	name.get(verNS, portID);
    }

    return true;
}



// *****************************************************************************
// CallbacksOut::getTermName()
//
// This function produces the name of the given terminal as a valid port
// identifier for IEEE 1364-2001 Verilog.  If the terminal is a bus terminal
// and the terminal represents the full range of the bus, the terminal name
// is taken from the name of the busDef of the terminal.
// *****************************************************************************
void
CallbacksOut::getTermName(const	oaModTerm   *term,
			  oaName	    &name)
{
    oaModBusTermDef *busDef = NULL;

    switch (term->getType()) {
      case oacModBusTermType:
	busDef = ((oaModBusTerm*) term)->getDef();
	break;

      case oacModBusTermBitType:
	busDef = ((oaModBusTermBit*) term)->getDef();
	break;
    }

    if (busDef && term->getNumBits() == busDef->getNumBits()) {
	oaScalarName    base;
	busDef->getName(base);
	name = base;
    } else {
	term->getName(name);
    }
}



// *****************************************************************************
// CallbacksOut::nameToPortID()
//
// This function transforms the given oaName into a valid port identifier for
// IEEE 1364-2001 Verilog.  Scalar names are left untouched.  All other names
// return the empty string which will cause the connection to be made by 
// order.
// *****************************************************************************
void
CallbacksOut::nameToPortID(const oaName	&name,
			   oaString	&portID)
{
    oaString	original;

    switch (name.getType()) {
      case oacScalarNameType:
	name.get(verNS, portID);
	break;

      default:
	portID = "";
	break;
    }
}



// *****************************************************************************
// CallbacksOut::nameToNetExpr()
//
// This function transforms the given oaName into a valid net expression for
// IEEE 1364-2001 Verilog. Scalar, vector and vector bit names are left
// untouched (unless they represent a global name in which case the global
// module name is added as a prefix). Bundle names are transformed into Verilog
// concatenations or numerical constants (as appropriate). This function may be
// called while producing a name with a the numerical prefix. It returns a
// NetExprType that is used to determine what prefix (if any) is appropriate
// and when to produce separator characters for bundle elements.
// *****************************************************************************
NetExprType
CallbacksOut::nameToNetExpr(const oaName    &name,
			    oaString	    &netExpr,
			    oaModule	    *module,
			    oaBoolean	    isGlobal,
			    oaSigTypeEnum   sigType)
{
    NetExprType	type = NameIsNet;

    switch (name.getType()) {
      case oacScalarNameType:
	name.get(verNS, netExpr);

	if (isTieHigh(netExpr, isGlobal, sigType)) {
	    netExpr = "1";
	    type = NameOneTicBOne;
	} else if (isTieLow(netExpr, isGlobal, sigType)) {
	    netExpr = "0";
	    type = NameOneTicBZero;
	}
	break;

      case oacVectorNameType:
      case oacVectorBitNameType:
	name.get(verNS, netExpr);
	break;

      case oacBundleNameType:
	return bundleToNetExpr(*name.getBundle(), netExpr, module);
    }

    if (isGlobal && type == NameIsNet) {
	netExpr = options.getGlobalModuleName() + hierSep + netExpr;
    }

    return type;
}



// *****************************************************************************
// CallbacksOut::bundleToNetExpr()
//
// This function transforms the given oaBundleName into a valid net expression
// for IEEE 1364-2001 Verilog. If the bundle consists of the tie high and 
// tie low net names, then a numerical constant is produced.  Otherwise, 
// a Verilog concatenation is produced.
// *****************************************************************************
NetExprType
CallbacksOut::bundleToNetExpr(const oaBundleName    &name,
			      oaString		    &netExpr,
			      oaModule		    *module)
{
    oaString	numExpr;
    oaString	memExpr;
    oaModNet	*memNet = oaModNet::find(module, name[0]);
    oaBoolean	isGlobal = memNet ? memNet->isGlobal() : false;
    oaSigType	sigType = memNet ? memNet->getSigType() 
				 : oaSigType(oacSignalSigType);
    NetExprType	memType = nameToNetExpr(name[0], memExpr, module, isGlobal, 
					sigType);
    NetExprType	returnType;
    NetExprType lastType;
    oaUInt4	nbits;
    oaBoolean	addedSep = false;

    initConcat(memType, memExpr, name[0].getRepeat(), netExpr, numExpr, nbits,
	       lastType, addedSep);

    returnType = lastType;

    for (oaUInt4 i = 1; i < name.getNumMembers(); i++) {
	memNet = oaModNet::find(module, name[i]);
	isGlobal = memNet ? memNet->isGlobal() : false;
	sigType = memNet ? memNet->getSigType() 
			 : oaSigType(oacSignalSigType);
	memType = nameToNetExpr(name[i], memExpr, module, isGlobal, sigType);
	combineMembers(memType, lastType, memExpr, netExpr, numExpr, 
		       name[i].getRepeat(), nbits, addedSep);

	if (returnType != NameIsNet) {
	    returnType = lastType;
	}
    }

    if (!numExpr.isEmpty()) {
	addNumPrefix(numExpr, netExpr, nbits, addedSep);
    }

    if (returnType == NameIsNet
	&& (name.getNumMembers() != 1 || name[0].getRepeat() != 1)) {
	netExpr = concatPrefix + netExpr + concatSuffix;
    }

    return returnType;
}