oaverilogcallbacksout.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// CallbacksOut::writeBody()
//
// This function writes the Verilog module body for the given OpenAccess module.
// The body will consist of all module instantiations and net constant 
// assignments.
// *****************************************************************************
void
CallbacksOut::writeBody(oaModule    &cell)
{
    incIndent();
    writeAssignments(cell);

    if (!cell.getInsts().isEmpty()) {
	write("\n");
    }

    oaBoolean		first = true;
    oaString		instName;
    oaScalarName	cellName;
    oaString		cellNameStr;
    oaIter<oaModInst>	iIter(cell.getInsts());

    while (oaModInst *inst = iIter.getNext()) {
        inst->getName(verNS, instName);

	if (inst->isModModuleInst() && inst->getMasterModule()) {
	    inst->getMasterModule()->getName(cellName);
	    cellName.get(verNS, cellNameStr);
	    writeIndent("%s %s", (const char*) cellNameStr, 
		        (const char*) instName);
	} else if (inst->isModDesignInst()) {
	    ((oaModDesignInst*) inst)->getCellName(verNS, cellNameStr);
	    writeIndent("%s %s", (const char*) cellNameStr, 
			(const char*) instName);
	} else {
	    continue;
	}

        incIndent();
	writeInstConnections(cell, inst);
        decIndent();
    }

    decIndent();
}



// *****************************************************************************
// CallbacksOut::writeAssignments()
//
// This function writes the net constant assignment statements for all
// OpenAccess nets that have equivalent nets.
// *****************************************************************************
void
CallbacksOut::writeAssignments(oaModule	&cell)
{
    oaIter<oaModNet>	netIter(cell.getNets());
    oaBoolean		first = true;

    while (oaModNet *net = netIter.getNext()) {
	if (!net->isModBitNet() || netPrinted->get(net) == Printed 
	    || ((oaModBitNet*) net)->getEquivalentNets().isEmpty() 
	    || isTieHigh((oaModBitNet*) net) || isTieLow((oaModBitNet*) net)) {
	    continue;
	}

	oaModBitNet *bitNet = (oaModBitNet*) net;

	if (bitNet->getType() == oacModBusNetBitType
	    && isBusNumAssignment(((oaModBusNetBit*) bitNet)->getDef())) {

	    writeBusNumAssignment(((oaModBusNetBit*) bitNet)->getDef(),
				  first);
	} else {
	    writeLocalAssignments(bitNet, first);
	}
    }

    netPrinted->remove(cell.getDesign());
}



// *****************************************************************************
// CallbacksOut::isBusNumAssignment()
//
// This function returns true if all the busNetBits of the given busNetDef are
// equivalent to nets that represent the tie high and tie low signals.
// *****************************************************************************
oaBoolean
CallbacksOut::isBusNumAssignment(oaModBusNetDef	*bus) const
{
    oaIter<oaModBusNetBit>	bitIter(bus->getBusNetBits());

    while (oaModBusNetBit   *bit = bitIter.getNext()) {
	oaModBitNet *equiv = bit->getPreferredEquivalent();

	if (!isTieHigh(equiv) && !isTieLow(equiv)) {
	    return false;
	}
    }

    return true;
}



// *****************************************************************************
// CallbacksOut::writeBusNumAssignment()
//
// This function writes the net constant assignment statement for equivalent 
// nets in the case where a given bus is assigned a numerical value.  In this 
// case, a single assign statement covering the entire range is produced and
// the right hand side of the assign statement is a single numerical value.
// *****************************************************************************
void
CallbacksOut::writeBusNumAssignment(oaModBusNetDef  *bus,
				    oaBoolean	    &first)
{
    oaScalarName    baseName;
    oaString	    lhsNameStr;

    bus->getName(baseName);
    baseName.get(verNS, lhsNameStr);

    oaUInt4 lsb = bus->getMinIndex();
    oaUInt4 msb = bus->getMaxIndex();
    oaInt4  inc = 1;

    if (bus->getBitOrder() == oacDescendingBitOrder) {
	oaUInt4	tmp = lsb;

	lsb = msb;
	msb = tmp;
	inc = -1;
    }

    oaString  rhsNameStr(64);

    rhsNameStr.format("%d'b", bus->getMaxIndex() - bus->getMinIndex() + 1);
    rhsNameStr.resize(rhsNameStr.getLength() + bus->getNumBits());

    oaModule	*module = bus->getModule();    
    oaUInt4	index = lsb;

    for (oaUInt4 i = 0; i < bus->getNumBits(); i++) {
	oaModBusNetBit	*bit = oaModBusNetBit::find(module, baseName, index);
	
	netPrinted->set(bit, Printed);
	
	if (isTieHigh(bit->getPreferredEquivalent())) {
	    rhsNameStr += "1";
	} else {
	    rhsNameStr += "0";
	}

	index += inc;
    }

    writeAssignment(lhsNameStr, rhsNameStr, first);
}



// *****************************************************************************
// CallbacksOut::writeLocalAssignments()
//
// This function writes the net constant assignment statement for equivalent 
// nets in the case where the given net is not a busNetBit or the preferred
// equivalent net does not exist or is not a global net.
// *****************************************************************************
void
CallbacksOut::writeLocalAssignments(oaModBitNet	*net,
				    oaBoolean	&first)
{
    oaName		    lhsName;
    oaString		    lhsNameStr;
    oaName		    rhsName;
    oaString		    rhsNameStr;
    std::set<oaModBitNet*>  inputs;
    std::set<oaModBitNet*>  outputs;

    binEquivNets(net, inputs, outputs);

    oaModBitNet *lhs = NULL;
    oaModBitNet *rhs = NULL;
    oaModBitNet *tmp = NULL;

    for (std::set<oaModBitNet*>::iterator outputIter = outputs.begin(); 
	 outputIter != outputs.end(); outputIter++) {

	lhs = rhs;
	rhs = *outputIter;
	netPrinted->set(rhs, Printed);

	if (lhs && rhs) {
	    if (lhs->isGlobal()) {
		tmp = lhs;
		lhs = rhs;
		rhs = tmp;
	    }

	    getNetExpr(lhs, lhsNameStr);
	    getNetExpr(rhs, rhsNameStr);
	    writeAssignment(lhsNameStr, rhsNameStr, first);

	    if (tmp) {
		rhs = lhs;
		tmp = NULL;
	    }
	}
    }

    for (std::set<oaModBitNet*>::iterator inputIter = inputs.begin(); 
	 inputIter != inputs.end(); inputIter++) {

	lhs = rhs;
	rhs = *inputIter;
	netPrinted->set(rhs, Printed);

	if (lhs && rhs) {
	    if (lhs->isGlobal()) {
		tmp = lhs;
		lhs = rhs;
		rhs = tmp;
	    }

	    getNetExpr(lhs, lhsNameStr);
	    getNetExpr(rhs, rhsNameStr);
	    writeAssignment(lhsNameStr, rhsNameStr, first);

	    if (tmp) {
		rhs = lhs;
		tmp = NULL;
	    }
	}
    }
}

// *****************************************************************************
// CallbacksOut::writeAssignment()
//
// This function writes an assignment statement to the equNetName from the 
// fromNetName.
// *****************************************************************************
void
CallbacksOut::writeAssignment(const oaString	&equNetName,
			      const oaString	&fromNetName,
			      oaBoolean		&first)
{
    if (first) {
	writeIndent("\n");
	first = false;
    }

    writeIndent("%s %s = %s;\n", (const char*) assignKeyword,
	        (const char*) equNetName, (const char*) fromNetName);
}



// *****************************************************************************
// CallbacksOut::writeInstConnections()
//
// This function writes the port connections for a module instantiation.
// The "cell" is the module that contains the instantiation.
// *****************************************************************************
void       
CallbacksOut::writeInstConnections(oaModule	&cell,
				   oaModInst	*inst)
{
    if ((inst->isModDesignInst() && ((oaModDesignInst*) inst)->getMaster() 
	 || inst->isModModuleInst()) && inst->getMasterModule()) {
	orderTerms(*inst->getMasterModule());
	writeBoundInstConnections(*inst);
    } else {
	orderInstTerms(*inst);
	writeUnboundInstConnections();
    }
}



// *****************************************************************************
// CallbacksOut::writeBoundInstConnections()
//
// This function writes connections of a bound instance. This function assumes
// that the inst terms and the terms of the master have been sorted.
// *****************************************************************************
void       
CallbacksOut::writeBoundInstConnections(oaModInst   &inst)
{
    oaBoolean	    first = true;
    TermIter	    termIter = terms.begin();
    oaString	    portID;
    oaString	    netExpr;

    incIndent();

    Connection	    connection;
    ConnectionList  connList;
    oaBoolean	    byPosition = false;
    oaModule	    *master = inst.getMasterModule();
    oaName	    termName;
    oaName	    netName;
    oaName	    emptyName;
    oaUInt4	    nameSeed = 0;
    
    for (TermIter iter = terms.begin(); iter != terms.end(); iter++) {
	oaModTerm	*term = *iter;
	oaModInstTerm   *iterm;
	oaBoolean	connected = false;

	if (options.testPreserveInterface() && !term->isInterface()) {
	    continue;
	}

	getTermName(term, termName);
	nameToPortID(termName, portID);

	if (inst.usesTermPositions()) {
	    iterm = oaModInstTerm::find(&inst, term->getPosition());
	} else {
	    iterm = oaModInstTerm::find(&inst, term);
	}

	if (iterm && iterm->getNet()) {
	    getNetExpr(iterm->getNet(), netExpr);
	    connected = true;
	} else {
	    oaName  connName;

	    for (oaUInt4 i = 0; i < term->getNumBits(); i++) {
		oaModBitTerm	*bit = term->getBit(i);

		if (inst.usesTermPositions()) {
		    iterm = oaModInstTerm::find(&inst, bit->getPosition());
		} else {
		    iterm = oaModInstTerm::find(&inst, bit);
		}

		if (iterm) {
		    oaModNet	*net = iterm->getNet();

		    if (net) {
			getNetName(net, netName);
			connected = true;
		    } else {
			Options::makeUniqueNetName(inst.getModule(), emptyName,
						   netName, nameSeed++);
		    }
		} else {
		    Options::makeUniqueNetName(inst.getModule(), emptyName,
					       netName, nameSeed++);
		}

		appendToName(netName, connName);
	    }

	    nameToNetExpr(connName, netExpr, inst.getModule());
	}

	if (connected) {
	    if (portID.isEmpty()) {
		connection.init(netExpr, term->getPosition());
		byPosition = true;
	    } else {
		connection.init(portID, netExpr);
	    }

	    connList.insert(connection);
	}
    }

    if (byPosition) {
	writeConnsByPosition(connList);
    } else {
	writeConns(connList);
    }
}



// *****************************************************************************
// CallbacksOut::writeUnboundInstConnections()
//
// This function writes connections of a bound instance. This function assumes
// that the inst terms have already been sorted using the orderInstTerms method.
// *****************************************************************************
void       
CallbacksOut::writeUnboundInstConnections()
{
    oaBoolean	    first = true;
    InstTermIter    termIter = iterms.begin();
    oaString	    portID;
    oaString	    netExpr;

    incIndent();

    Connection	    connection;
    ConnectionList  connList;
    oaBoolean	    byPosition = false;

    while (getNextPortNet(termIter, connection)) {
	connList.insert(connection);
	byPosition = byPosition || connection.isByPosition();
    }

    if (byPosition) {
	writeConnsByPosition(connList);
    } else {
	writeConns(connList);
    }
}



// *****************************************************************************
// CallbacksOut::writeConns()
//
// Given a list of connections, this function write the connections as a set
// of named connections.
// *****************************************************************************
void       
CallbacksOut::writeConns(ConnectionList    &connList) 
{    
    oaUInt4	lastPosition = oacNullIndex;
    oaBoolean	first = true;

    for (ConnectionListIter iter = connList.begin(); iter != connList.end(); 
	 iter++) {

	if (first) {
	    write(" (\n");
	}

	if (!first) {
	    write(",\n");
	}

	writeHierConn((*iter)->getPort(), (*iter)->getNet());

	first = false;
	lastPosition = (*iter)->getPosition();
    }

    if (first) {
	write(" (");
    }