oaverilogcallbacksout.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogCallbacksOut.cpp
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this material may not be copied, modified,
// re-published, uploaded, executed, or distributed in any way, in any medium,
// in whole or in part, without prior written permission from Cadence.
//
//                Copyright 2002-2005 Cadence Design Systems, Inc.
//         (c) Copyright 2003 Hewlett-Packard Development Company, LP
//                           All Rights Reserved.
//
//  $Author: sailajad $
//  $Revision: 1.48 $
//  $Date: 2005/07/17 21:07:32 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************




#include "oaVerilogOutPvt.h"

BEGIN_VERILOG_NAMESPACE



// *****************************************************************************
// Initialize static data members.
// *****************************************************************************
const oaString	CallbacksOut::languageName("Verilog");
const oaString	CallbacksOut::languageVersion("2001");
const oaString	CallbacksOut::commentPrefix("//");
const oaString	CallbacksOut::commentSuffix("");

const oaString	CallbacksOut::moduleKeyword("module");
const oaString	CallbacksOut::endModuleKeyword("endmodule");
const oaString	CallbacksOut::assignKeyword("assign");
const oaString	CallbacksOut::inputKeyword("input");
const oaString	CallbacksOut::outputKeyword("output");
const oaString	CallbacksOut::inoutKeyword("inout");
const oaString	CallbacksOut::supply0Keyword("supply0");
const oaString	CallbacksOut::supply1Keyword("supply1");
const oaString	CallbacksOut::wireKeyword("wire");
const oaString	CallbacksOut::binaryPrefix("'b");
const oaString	CallbacksOut::oneTicBOne("1'b1");
const oaString	CallbacksOut::oneTicBZero("1'b0");
const oaString	CallbacksOut::hierSep(".");
const oaString	CallbacksOut::concatPrefix("{");
const oaString	CallbacksOut::concatSep(",");
const oaString	CallbacksOut::concatSuffix("}");
const oaString	CallbacksOut::rangePrefix("[");
const oaString	CallbacksOut::rangeSep(":");
const oaString	CallbacksOut::rangeSuffix("]");
const oaString	CallbacksOut::escapePrefix("\\");
const oaString	CallbacksOut::escapeSuffix(" ");



// *****************************************************************************
// CallbacksOut::CallbacksOut()
//
// This is the constructor of the CallbacksOut.
// *****************************************************************************
CallbacksOut::CallbacksOut(OptionsOut	    &optIn,
			   const oaString   *version)
:   WriterCallback(optIn.getFileName(), verNS, languageName, 
		   version ? *version : languageVersion, commentPrefix,
		   commentSuffix),
    globalCell(NULL),
    options(optIn)
{   
    busTermPrinted = oaIntAppDef<oaModBusTermDef>::get(optIn.busTermPrintedName, 
						       NotPrinted, false);
    termPrinted = oaIntAppDef<oaModTerm>::get(optIn.termPrintedName, NotPrinted, 
					      false);
    busNetPrinted = oaIntAppDef<oaModBusNetDef>::get(optIn.busNetPrintedName, 
						     NotPrinted, false);
    netPrinted = oaIntAppDef<oaModNet>::get(optIn.netPrintedName, 
					    NotPrinted, false);
    itermPrinted = oaIntAppDef<oaModInstTerm>::get(optIn.itermPrintedName,
						   NotPrinted, false);
    termPosition = oaIntAppDef<oaModTerm>::get(optIn.termPositionName, 
					       oacNullIndex, false);
}



// *****************************************************************************
// CallbacksOut::CallbacksOut()
//
// This is the destructor of the CallbacksOut.
// *****************************************************************************
CallbacksOut::~CallbacksOut()
{
}



// *****************************************************************************
// CallbacksOut::writeCell()
// 
// This function is the main entry point for producing the Verilog netlist of
// the given module.
// *****************************************************************************
void
CallbacksOut::writeCell(oaModule    &cell)
{
    oaSimpleName    tie0;
    oaSimpleName    tie1;

    options.getTieLowNetBase(tie0);
    options.getTieHighNetBase(tie1);
    tie0.get(verNS, tieLowNetStr);
    tie1.get(verNS, tieHighNetStr);

    tieHighNet = oaModNet::find(&cell, tie1);
    tieLowNet = oaModNet::find(&cell, tie0);

    if (tieHighNet && !tieHighNet->isGlobal()) {
	tieHighNet = NULL;
    }

    if (tieLowNet && !tieLowNet->isGlobal()) {
	tieLowNet = NULL;
    }

    orderTerms(cell);
    writeModule(cell);
    writeInterface(cell);
    writeWire(cell);
    writeBody(cell);
    writeEndModule(cell);

    termPrinted->remove(cell.getDesign());
    busTermPrinted->remove(cell.getDesign());
    netPrinted->remove(cell.getDesign());
    busNetPrinted->remove(cell.getDesign());
    itermPrinted->remove(cell.getDesign());
    termPosition->remove(cell.getDesign());
}



// *****************************************************************************
// CallbacksOut::writeModule()
//
// This functions writes the Verilog module declaration and module port list 
// for the given OpenAccess Module.
// *****************************************************************************
void
CallbacksOut::writeModule(oaModule  &cell)
{
    oaString	    moduleName;
    oaString	    termName;
    oaScalarName    scalarModName;

    cell.getName(scalarModName);
    scalarModName.get(verNS, moduleName);
    
    write("\n%s %s ", (const char*) moduleKeyword, 
	  (const char*)moduleName);

    incIndent();
    writePortList(cell);
    decIndent();

    termPrinted->remove(cell.getDesign());
    busTermPrinted->remove(cell.getDesign());
}



// *****************************************************************************
// CallbacksOut::writePortList()
//
// This functions writes the Verilog module port list for the given OpenAccess
// module.  This function assumes that the terminals have already been sorted
// using the orderTerms method.
// *****************************************************************************
void
CallbacksOut::writePortList(oaModule	&cell)
{
    oaBoolean	first = true;
    TermIter	termIter = terms.begin();
    oaString	termName;
    oaString	netName;

    write("(");
    while (getNextPortNet(termIter, termName, netName)) {
	if (first) {
	    write("\n");
	    first = false;
	} else {
	    write(",\n");
	}

	if (termName != netName) {
	    writePortAlias(termName, netName);
	} else {
	    writePort(termName);
	}
    }
    write(");\n");
}



// *****************************************************************************
// CallbacksOut::writePortAlias()
//
// This functions a port alias expression.
// *****************************************************************************
void
CallbacksOut::writePortAlias(const oaString &portID,
			     const oaString &netExpr) const
{
    writeIndent("%s%s(%s)", (const char*) hierSep, (const char*) portID, 
	        (const char*) netExpr);
}



// *****************************************************************************
// CallbacksOut::writePort()
//
// This functions a simple port identifier.
// *****************************************************************************
void
CallbacksOut::writePort(const oaString	&portID) const
{
    writeIndent("%s", (const char*) portID);
}



// *****************************************************************************
// CallbacksOut::writeInterface()
// 
// This functions writes module interface for the given OpenAccess module. The 
// module interface is the set of all port declaration for the module.
// *****************************************************************************
void
CallbacksOut::writeInterface(oaModule	&cell)
{
    writePortDeclarationsSection();
    termPrinted->remove(cell.getDesign());
    busTermPrinted->remove(cell.getDesign());
}



// *****************************************************************************
// CallbacksOut::writePortDeclarationSection()
//
// This function writes the port declarations section of the module.  It 
// assumes that the ports have been sorted using the orderTerms method.
// *****************************************************************************
void       
CallbacksOut::writePortDeclarationsSection()
{
    incIndent();

    oaString	termName;
    TermIter	termIter;
    oaBoolean	first = true;

    if (terms.size() > 0) {
	write("\n");
    }

    for (termIter = terms.begin(); termIter != terms.end(); termIter++) {
	if (testProduceTerm(*termIter)) {
	    writePortDeclaration(*termIter, termName);
	}
    }
    
    decIndent();
}



// *****************************************************************************
// CallbacksOut::writePortDeclaration()
//
// This functions prints a port declaration statement for a single terminal.
// *****************************************************************************
void       
CallbacksOut::writePortDeclaration(oaModTerm	*term,
				   oaString	&termName)
{
    if (term->getNet()->getType() == oacModBundleNetType) {
	oaModBundleNet	    *bundle = (oaModBundleNet*) term->getNet();
	oaIter<oaModNet>    memIter(bundle->getMembers());

	while (oaModNet *net = memIter.getNext()) {
	    writePortNetDeclaration(term->getTermType(), net, termName);
	}
    } else {
	writePortNetDeclaration(term->getTermType(), term->getNet(), termName);
    }
}



// *****************************************************************************
// CallbacksOut::writePortNetDeclaration()
//
// This functions prints a single net declaration associated with a terminal.
// *****************************************************************************
void       
CallbacksOut::writePortNetDeclaration(oaTermTypeEnum	termType,
				      oaModNet		*net,
				      oaString		&netName)
{
    if (netPrinted->get(net) == Printed) {
	return;
    }

    oaType	    type = net->getType();
    oaModBusNetDef  *netDef;

    if (type == oacModBusNetType) {
	netDef = ((oaModBusNet*) net)->getDef();
    } else if (type == oacModBusNetBitType) {
	netDef = ((oaModBusNetBit*) net)->getDef();
    } else {
	netDef = NULL;
    }

    if (netDef) {
	if (!getBusNetDecl(netDef, netName)) {
	    return;
	}
    } else {
	net->getName(verNS, netName);
    }

    if (netName.isEmpty()) {
	return;
    }

    switch (termType) {
      case oacSwitchTermType:
      case oacInputTermType:
	  writeIndent("%s %s;\n", (const char*) inputKeyword,
		      (const char*) netName);
	  break;

      case oacOutputTermType:
      case oacTristateTermType:
	  writeIndent("%s %s;\n", (const char*) outputKeyword,
		      (const char*) netName);
	  break;

      case oacInputOutputTermType:
	  writeIndent("%s %s;\n", (const char*) inoutKeyword,
		      (const char*) netName);
	  break;
    }

    netPrinted->set(net, Printed);

    if (netDef) {
	busNetPrinted->set(netDef, Printed);
    }
}



// *****************************************************************************
// CallbacksOut::writeWire()
// 
// This functions writes the wire declarations for the given module. Global
// nets are not declared locally.  Wires that were previously declared as ports
// are not re-declared.
// *****************************************************************************
void
CallbacksOut::writeWire(oaModule    &cell)
{
    if (!cell.getNets().isEmpty()) {
	write("\n");
    }

    incIndent();

    oaName		name;
    oaString		netName;
    const oaString	*wireType;
    oaIter<oaModNet>    nIter(cell.getNets());
    oaModNet		*net;

    while (net = nIter.getNext()) {
	if (net->isGlobal() || netPrinted->get(net) == Printed) {
	    continue;
	}

	net->getName(name);

	switch (net->getType()) {
	  case oacModBusNetType:
	    if (!getBusNetDecl(((oaModBusNet*) net)->getDef(), netName)) {
		continue;
	    }
	    break;

	  case oacModBusNetBitType:
	    if (!getBusNetDecl(((oaModBusNetBit*) net)->getDef(), netName)) {
		continue;
	    }
	    break;

	  case oacModBundleNetType:
	    continue;
	    break;

	  default:
	    net->getName(verNS, netName);
	    break;
	}

        switch (net->getSigType()) {
          case oacTieHiSigType :
          case oacPowerSigType :
	    wireType = &supply1Keyword;
	    break;
          
	  case oacTieLoSigType :
          case oacGroundSigType :
	    wireType = &supply0Keyword;
	    break;

	  case oacSignalSigType :
          case oacClockSigType :
          case oacTieoffSigType :
          case oacAnalogSigType :
          case oacScanSigType :
          case oacResetSigType :
	    wireType = &wireKeyword;
	    break;
        }

	writeIndent("%s %s;\n", (const char*) (*wireType), 
		    (const char*) netName);
    }

    decIndent();
    netPrinted->remove(cell.getDesign());
}