oaverilogtypes.h

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogTypes.h
//
// This file defines the base types used by the Verilog translator.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this material may not be copied, modified,
// re-published, uploaded, executed, or distributed in any way, in any medium,
// in whole or in part, without prior written permission from Cadence.
//
//                Copyright 2003-2005 Cadence Design Systems, Inc.
//                           All Rights Reserved.
//
//  $Author: shellye $
//  $Revision: 1.17 $
//  $Date: 2005/05/17 01:43:59 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#ifndef oaVerilogTypes_P
#define oaVerilogTypes_P



#include <algorithm>
#include <set>
#include <list>
#include <vector>
#include <stdio.h>

#include "oaDesignDB.h"



// *****************************************************************************
// Define the DLL interface
// *****************************************************************************
#define	OA_VERILOG_DLL_API



// *****************************************************************************
// Define the namespace macros
// *****************************************************************************
#define BEGIN_VERILOG_NAMESPACE namespace oaVerilog { using namespace oa;
#define END_VERILOG_NAMESPACE }



// *****************************************************************************
// Forward class declarations
// *****************************************************************************
BEGIN_VERILOG_NAMESPACE

class Error;
class CallbacksIn;
class CallbacksOut;
class LeafMgr;
class ModuleCallbacksIn;
class NameList;
class ParamList;
class Options;
class OptionsIn;
class OptionsOut;
class Parser;
class ParserBase;
class Range;
class RangeList;
class Scanner;
class Value;
class ValueList;
class VerilogIn;
class VerilogOut;
class WriterCallback;

typedef std::list<oaDesign*>		    DesignList;
typedef std::list<oaDesign*>::iterator	    DesignListIter;
typedef std::list<oaString*>		    StringList;
typedef std::list<oaString*>::iterator	    StringListIter;
typedef	std::list<oaScalarName*>	    ScalarNameList;
typedef	std::list<oaScalarName*>::iterator  ScalarNameListIter;


END_VERILOG_NAMESPACE

#endif