oaverilogcallbacksin.cpp

openaccess与verilog互相转化时所用的源代码

	    makeUniqueTermName(currentModule, oaName(termName), termName);
	    term = NULL;
	}

	// If the type of the parameter is a string and if that string length
	// is greater than 0 then the parameter value represents the name of
	// the connecting net. Otherwise, there is no net to connect to. This
	// "terminal" is a placeholder with no real connectivity in the
	// module. However, a terminal must still be created as to preserve the
	// terminal order. To create the placeholder terminal, generate a
	// unique name based on the input terminal name.
	if ((*portIter)->getType() == oacStringParamType 
	    && strlen((*portIter)->getStringVal()) > 0)	{
	    Options::oaStringToName((*portIter)->getStringVal(), netName);
	} else {
	    makeUniqueNetName(currentModule, emptyName, netName);
	}

	net = getNet(netName, oacSignalSigType, NULL, NULL, true);
	net->getName(netName);

	// If the term is not NULL then the terminal was previously defined.
	// The defined terminal should be moved to the net. If the terminal
	// was not previously defined then it will be defined based on the net
	// it will be connected to. In that case a term name must be created
	// with the correct width and bit order.
	if (term) {
	    if (term->getNet() != net) { 
		moveToNet(term,	*net);
	    }
	} else {
	    switch (netName.getType()) {
	      case oacVectorNameType:
		getStartStopStep(*net, termStart, termStop, termStep);

		if (termName.getType() == oacScalarNameType) {
		    oaVectorName  busName(*termName.getScalar(), termStart,
					  termStop, 1);

		    termName = busName;
		}
		break;

	      case oacBundleNameType:
		if (termName.getType() == oacScalarNameType) {
		    oaVectorName busName(*termName.getScalar(),
					 0, netName.getNumBits() - 1, 1);

		    termName = busName;
		}
		break;
	    }

	    if (termNameNotEmpty) {
		makeUniqueTermName(currentModule, termName, termName);
	    } else {
		makeUniqueTermName(currentModule, emptyName, termName);
	    }

	    term = getPort(termName, net, oacUnusedTermType,  
			   net->getSigType(), NULL, NULL);
	    term->getName(termName);
	}

	term->unsetPosition();
	term->setPosition(index++);
	term->setIsInterface(true);
	termCreatedBy->set(term, false);
	
	if (term->getTermType() == oacUnusedTermType) {
	    term->setTermType(oacInputOutputTermType);
	}

	i++;
    }
}



// *****************************************************************************
// CallbacksIn::evalBinaryOpExpr()
//
// Given two values and and operator, evaluate the given expression and store
// the result in "result"
// *****************************************************************************
void
CallbacksIn::evalBinaryOpExpr(const Value	&lexp,
			      const oaString	&op,
			      const Value	&rexp,
			      Value		&result)
{
    notImplemented(BinaryOpImpl);

    result = lexp;
}



// *****************************************************************************
// CallbacksIn::evalCondExpr()
//
// Given a result of a test (testCase value) and a list of attributes, select
// either the "caseTrue" or the "caseFalse" value and store the result in
// "result"
// *****************************************************************************
void
CallbacksIn::evalCondExpr(const	Value	    &testCase,
			  const	ParamList   &attr,
			  const	Value	    &caseTrue,
			  const	Value	    &caseFalse,
			  Value		    &result)
{
    if (testCase.toInt() != 0) {
	result = caseTrue;
    } else {
	result = caseFalse;
    }
}



// *****************************************************************************
// CallbacksIn::evalMinTypMaxExpr()
//
// This function evaluates a min:typ:max expression and store the result in 
// "result"
// *****************************************************************************
void
CallbacksIn::evalMinTypMaxExpr(const Value    &min,
				      const Value    &typ,
				      const Value    &max,
				      Value	    &result)
{
    Error  warn(MinTypMaxExpr, fileAndLine);

    warning(warn);
    result = typ;
}



// *****************************************************************************
// CallbacksIn::evalUnaryOpExpr()
//
// This function evaluates a unary operator on the given value (expr) and store
// the result in "result"
// *****************************************************************************
void
CallbacksIn::evalUnaryOpExpr(const oaString	&op,
				    const Value	&expr,
				    Value	&result)
{
    notImplemented(UnaryOpImpl);

    result = expr;
}



// *****************************************************************************
// CallbacksIn::eventDeclaration()
//
// This function handles event declarations.
// *****************************************************************************
void
CallbacksIn::eventDeclaration()
{
    notImplemented(EventDeclImpl);
}



// *****************************************************************************
// CallbacksIn::expandCreateInstTerm()
//
// The Verilog language allows single bit nets to connect to single bit terms
// of multi-bit instances. These functions expand the single bit net to fit 
// the intended width of the connection when the connected instance is a 
// ModModuleVectorInst. The first function connects by name. The second 
// function connects by position.
// *****************************************************************************
void
CallbacksIn::expandCreateInstTerm(oaModVectorInst   *inst,
				  oaModNet	    *net,
				  oaName	    &termName)
{
    if (net->getNumBits() == 1 && termName.getNumBits() == 1) {
	oaName		nName;
	oaString	nNameStr;

	net->getName(nName);
	nName.get(vns, nNameStr);

	oaSimpleName	bitName(vns, nNameStr);
	oaBundleName	bName(bitName, inst->getNumBits());
	oaModBundleNet	*bNet =	oaModBundleNet::find(currentModule, bName);

	if (!bNet) {
	    bNet = oaModBundleNet::create(currentModule, bName,
					  net->getSigType(), net->isGlobal());
	}

	createInstTerm(bNet, (oaModInst*) inst, termName);
    } else {
	createInstTerm(net, (oaModInst*) inst, termName);
    }
}

void
CallbacksIn::expandCreateInstTerm(oaModVectorInst   *inst,
				  oaModNet	    *net,
				  oaUInt4	    termPosition)
{
    if (net->getNumBits() == 1) {
	oaName		nName;
	oaString	nNameStr;

	net->getName(nName);
	nName.get(vns, nNameStr);

	oaSimpleName	bitName(vns, nNameStr);
	oaBundleName	bName(bitName, inst->getNumBits());
	oaModBundleNet	*bNet =	oaModBundleNet::find(currentModule, bName);

	if (!bNet) {
	    bNet = oaModBundleNet::create(currentModule, bName,
					  net->getSigType(), net->isGlobal());
	}

	createInstTerm(bNet, (oaModInst*) inst, termPosition);
    } else {
	createInstTerm(net, (oaModInst*) inst, termPosition);
    }
}



// *****************************************************************************
// CallbacksIn::expandITermScalarName()
//
// Given a scalar name (nameIn) the connecting net and the connected instance,
// this method finds the terminal corresponding to the given name and stores the
// terminal name in nameOut. Even though the input name is a scalar, it may be
// the base name of a bus in which case the output name will be a vector name 
// representing the entire bus. If no master is available then scalar names
// will inherit their width and bit order from the connecting net.
// *****************************************************************************
void
CallbacksIn::expandITermScalarName(const oaScalarName	&nameIn,
				   const oaModNet	&net,
				   const oaModInst	&inst,
				   oaName		&nameOut)
{
    oaModule	*master	= (const_cast<oaModInst&>(inst)).getMasterModule();
    
    if (master) {
	oaModTerm   *term = oaModScalarTerm::find(master, nameIn);

	if (term) {
	    nameOut = nameIn;
	    return;
	} else {
	    oaModBusTermDef *busTermDef = oaModBusTermDef::find(master, nameIn);

	    if (busTermDef) {
		oaUInt4	minIndex = busTermDef->getMinIndex();
		oaUInt4 maxIndex = busTermDef->getMaxIndex();

		if (busTermDef->getBitOrder() == oacAscendingBitOrder) {
		    oaVectorName    busName(nameIn, minIndex, maxIndex);

		    nameOut = busName;
		} else {
		    if (minIndex == maxIndex) {
			oaVectorBitName busName(nameIn, minIndex);

			nameOut = busName;
		    } else {
			oaVectorName    busName(nameIn, maxIndex, minIndex);

			nameOut = busName;
		    }
		}

		return;
	    }
	}
    }
    
    if (net.getNumBits() > 1 && net.getNumBits() != inst.getNumBits()) {
	oaUInt4	width = net.getNumBits() / inst.getNumBits();
	oaUInt4	start;
	oaUInt4 stop;

	if (net.getType() == oacModBusNetType) {
	    oaInt4  step;

	    getStartStopStep(net, start, stop, step);

	    if (start < stop) {
		stop = width - 1;
		start = 0;
	    } else {
		start = width - 1;
		stop = 0;
	    }
	} else if (net.getType() == oacModBundleNetType) {
	    start = width - 1;
	    stop = 0;
	}

	oaVectorName    busName(nameIn, start, stop);

	nameOut = busName;
    } else {
	nameOut = nameIn;
    }
}



// *****************************************************************************
// CallbacksIn::expandNetBundleName()
//
// Given a bundle name of a net, this method expands each element of the bundle
// and forms a new bundle (nameOut) from the expanded element names. Since
// scalar names can represent entire busses, each scalar name can potentially
// be transformed into a vector name.
// *****************************************************************************
void
CallbacksIn::expandNetBundleName(const oaBundleName &nameIn,
				 oaBundleName	    &nameOut)
{
    oaBundleName    localNameIn(nameIn);
    oaName	    eltNameOut;
    oaSimpleName    eltNameIn;
    oaString	    eltNameInStr;

    for	(oaUInt4 i = 0;	i < localNameIn.getNumBits(); i++) {
	localNameIn.getBitName(vns, i, eltNameInStr);
	eltNameIn.init(vns, eltNameInStr);

	if (eltNameIn.getType()	== oacScalarNameType) {
	    expandNetScalarName(*eltNameIn.getScalar(),	NULL, eltNameOut);
	    switch (eltNameOut.getType()) {
	      case oacScalarNameType:
		nameOut.append(*eltNameOut.getScalar());
		break;

	      case oacVectorNameType:
		nameOut.append(*eltNameOut.getVector());
		break;

	      case oacVectorBitNameType:
		nameOut.append(*eltNameOut.getVectorBit());
		break;
	    }
	} else {
	    nameOut.append(eltNameIn);
	}
    }	    
}



// *****************************************************************************
// CallbacksIn::expandNetScalarName()
//
// Given a scalar name (nameIn) and an optional range, this method applies the
// given range to the name and store the result in nameOut. Despite being a
// scalar name, the input name (nameIn) could represent any of the following: 
//   1) a scalar net   
//   2) a scalar net with a range (IE: really a bus net) 
//   3) a scalar net with a range (IE: really a bus bit net) 
//   4) a scalar net without a range but representing an entire bus
// *****************************************************************************
void
CallbacksIn::expandNetScalarName(const oaScalarName &nameIn,
				 const Range	    *rangeOption,
				 oaName		    &nameOut)
{
    if (rangeOption) {
	if (rangeOption->getStopInt() == rangeOption->getStartInt()) {
	    // This represents state (3) in the header comment.
	    nameOut = oaVectorBitName(nameIn, rangeOption->getStopInt());
	} else {
	    // This represents state (2) in the header comment.
	    oaInt4  step = 1;
	    nameOut = oaVectorName(nameIn,
				   rangeOption->getStartInt(),
				   rangeOption->getStopInt(),
				   step);
	}
    } else {
	oaModBusNetDef	*bnDef = oaModBusNetDef::find(currentModule, nameIn);

	if (bnDef) {
	    // This represents state (4) in the header comment.
	    oaScalarName    defName;
	    oaUInt4	    start;
	    oaUInt4	    stop;
	    oaInt4	    step;

	    getStartStopStep(*bnDef, start, stop, step);
	    bnDef->getName(defName);

	    if (start == stop) {
		oaModBusNetBit	*bit = oaModBusNetBit::find(currentModule,
							    defName, start);
		bit->getName(nameOut);
	    } else {
		oaModBusNet *bus = oaModBusNet::find(currentModule, defName,
						     start, stop, 1);

		if (bus) {
		    bus->getName(nameOut);
		} else {
		    oaVectorName    busName(defName, start, stop, 1);

		    nameOut = busName;
		}
	    }
	} else {
	    // This represents state (1) in the header comment.
	    nameOut = nameIn;
	}
    }
}



// *****************************************************************************
// CallbacksIn::expandTermBundleName()
//
// Given a bundle name of a terminal, this method expands each element of the 
// bundle and forms a new bundle (nameOut) from the expanded element names. 
// Since scalar names can represent entire busses, each scalar name can 
// potentially be transformed into a vector name.
// *****************************************************************************
void
CallbacksIn::expandTermBundleName(const oaBundleName	&nameIn,
				  oaBundleName		&nameOut)
{
    oaName	    eltNameOut;
    oaSimpleName    eltNameIn;
    oaString	    eltNameInStr;

    for	(oaUInt4 i = 0;	i < nameIn.getNumBits(); i++) {
	nameIn.getBitName(vns, i, eltNameInStr);
	eltNameIn.init(vns, eltNameInStr);

	if (eltNameIn.getType()	== oacScalarNameType) {
	    expandTermScalarName(*eltNameIn.getScalar(), eltNameOut);

	    switch (eltNameOut.getType()) {
	      case oacScalarNameType: