oaverilogleafmgr.h

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogLeafMgr.h
//
// This file contains the definition for the LeafMgr class. This class
// implements a manager for leaf cells.  Leaf cells are defined as cells that
// are external to the modules that are created by the reader.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this material may not be copied, modified,
// re-published, uploaded, executed, or distributed in any way, in any medium,
// in whole or in part, without prior written permission from Cadence.
//
//		  Copyright 2003-2005 Cadence Design Systems, Inc.
//			     All Rights	Reserved.
//
//  $Author: shaun $
//  $Revision: 1.14 $
//  $Date: 2005/03/30 00:04:27 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#ifndef	oaVerilogLeafMgr_P
#define	oaVerilogLeafMgr_P

BEGIN_VERILOG_NAMESPACE
using namespace oaUtil;



// *****************************************************************************
// ModuleTypeEnum
// *****************************************************************************
enum ModuleTypeEnum {ModuleUnknownType		= 0,
		     ModuleCellType		= 1,
		     ModuleStubType		= 2,
		     ModuleUndefLeafType	= 3,
		     ModuleIncompleteLeafType	= 4,
		     ModuleBlackBoxLeafType	= 5,
		     ModuleLeafType		= 6
		    };



// *****************************************************************************
// LeafMgr
// *****************************************************************************
class OA_VERILOG_DLL_API LeafMgr {
  public:
			    LeafMgr(OptionsIn	&optIn);
			    ~LeafMgr();

    oaDesign		    *findLeaf(const oaScalarName    &cellName);
    oaBoolean		    isLeaf(const oaDesign   *design);
    oaBoolean		    isLeaf(const oaScalarName	&cellName);

    ModuleTypeEnum	    getType(const oaScalarName	&cellName);
    void		    setType(const oaScalarName	&cellName,
				    ModuleTypeEnum leafType);

    void		    setCallbacks(CallbacksIn	*init);
    void		    reset();

  protected:
    void		    clearLeafInfo();

    const oaVerilogNS	    vns;
    OptionsIn		    &options;
    oaUtil::HashTable<oaString, oaDesign*>	leafMap;
    oaUtil::HashTable<oaString,	ModuleTypeEnum>	leafClass;
    CallbacksIn		    *callbacks;
};



END_VERILOG_NAMESPACE

#endif