oaverilogout.cpp

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogOut.cpp
//
// This file contains the implementation of the VerilogOut class.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this material may not be copied, modified,
// re-published, uploaded, executed, or distributed in any way, in any medium,
// in whole or in part, without prior written permission from Cadence.
//
//                Copyright 2002-2005 Cadence Design Systems, Inc.
//         (c) Copyright 2003 Hewlett-Packard Development Company, LP
//                           All Rights Reserved.
//
//  $Author: shaun $
//  $Revision: 1.30 $
//  $Date: 2005/05/14 02:51:40 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#include "oaVerilogOutPvt.h"

BEGIN_VERILOG_NAMESPACE



// *****************************************************************************
// VerilogOut::VerilogOut()
//
// This is the constructor of the VerilogOut class.
// *****************************************************************************
VerilogOut::VerilogOut(MsgAdapter   &msgsIn)
: verilogCB(NULL),
  leafCB(NULL),
  topModule(NULL),
  status(true),
  options(msgsIn),
  defaultCallbacks(options),
  defaultLeafCallbacks(options),
  openedDesign(NULL)
{
    verilogCB = &defaultCallbacks;
    leafCB = &defaultLeafCallbacks;
    printedModule = oaIntAppDef<oaModule>::get(options.getPrintedModuleName(), 
					       NotPrinted, false);
    printedDesign = oaIntAppDef<oaDesign>::get(options.getPrintedDesignName(), 
					       NotPrinted, false);
}



// *****************************************************************************
// VerilogOut::~VerilogOut()
// *****************************************************************************
VerilogOut::~VerilogOut()
{
}



// *****************************************************************************
// VerilogOut::getOptions()
//
// This function opens the top design to produce for output.
// *****************************************************************************
OptionsOut&
VerilogOut::getOptions()
{
    return options;
}



// *****************************************************************************
// VerilogOut::setModuleCallbacks()
//
// This function sets the callbacks used to produce the Verilog netlist for
// modules.
// *****************************************************************************
void
VerilogOut::setModuleCallbacks(CallbacksOut *newCB)
{
    verilogCB = newCB;
}



// *****************************************************************************
// VerilogOut::setLeafCallbacks()
//
// This function sets the callbacks used to produce the Verilog netlist for
// leaf cells.
// *****************************************************************************
void
VerilogOut::setLeafCallbacks(CallbacksOut   *newCB)
{
    leafCB = newCB;
}



// *****************************************************************************
// VerilogOut::openDesign()
//
// This function opens the top design to produce for output.
// *****************************************************************************
void
VerilogOut::openDesign()
{   
    oaDesign	*design = oaDesign::find(options.getLibName(), 
					 options.getCellName(),
					 options.getViewName());
    
    if (!design) {
        openedDesign = oaDesign::open(options.getLibName(), 
				      options.getCellName(),
				      options.getViewName(), 'r');
	design = openedDesign;
    }
    
    topModule = design->getTopModule();
    
    if (!topModule) {
	oaString    libNameStr;
	oaString    cellNameStr;
	oaString    viewNameStr;

	options.getLibName().get(vns, libNameStr);
	options.getCellName().get(vns, cellNameStr);
	options.getViewName().get(vns, viewNameStr);

	throw Error(NoTopModule, NULL, (const char*) libNameStr,
		    (const char*) cellNameStr, (const char*) viewNameStr);
    }
}



// *****************************************************************************
// VerilogOut::closeDesign()
//
// This function closes the top design if it was opened by this component.
// *****************************************************************************
void
VerilogOut::closeDesign()
{   
    if (openedDesign) {
	openedDesign->close();
    }
}



// *****************************************************************************
// VerilogOut::write()
//
// This function run the Verilog write process. It will setup the writer
// callbacks and produce Verilog modules, bottom up, from the hierarchy.
// *****************************************************************************
void
VerilogOut::write()
{    
    openDesign();

    verilogCB->openOutput(options.getFileName());

    verilogCB->writeHeader(*topModule);

    if (options.testProduceLeaf() && !options.getLeafFile().isEmpty()) {
	leafCB->openOutput(options.getLeafFile());
	leafCB->writeHeader(*topModule);
    } else {
	leafCB = verilogCB;
    }

    if (options.testRecursiveDesign()) {
	walkDesignHier(topModule->getDesign());
    } else if (options.testRecursive()) {
	walkModuleHier(topModule);
    } else {
	writeCell(*topModule);
    }

    verilogCB->writeFooter(*topModule);

    if (leafCB != verilogCB) {
	leafCB->writeFooter(*topModule);
	leafCB->closeOutput();
    }

    verilogCB->closeOutput();

    closeDesign();
}



// *****************************************************************************
// VerilogOut::walkDesignHier
//
// This function walks the module and design hierarchy and produces a Verilog 
// representation for each module.
// *****************************************************************************
void
VerilogOut::walkDesignHier(oaDesign *top)
{
    oaModule	*topMod = top->getTopModule();

    if (topMod) {
	oaIter<oaModInstHeader>	ihdrIter(top->getModInstHeaders());

	while (oaModInstHeader	*ihdr = ihdrIter.getNext()) {
	    if (!ihdr->getMaster() 
		|| printedDesign->get(ihdr->getMaster()) == Printed
		|| ihdr->getInsts(oacInstIterNotImplicit, topMod).isEmpty()) {
		continue;
	    }

	    walkDesignHier(ihdr->getMaster());
	}

	walkModuleHier(topMod);
	printedDesign->set(top, Printed);
    }
}



// *****************************************************************************
// VerilogOut::walkModuleHier
//
// This function walks the module hierarchy and produces a Verilog 
// representation for each module.
// *****************************************************************************
void
VerilogOut::walkModuleHier(oaModule *top)
{
    if (printedModule->get(top) == Printed) {
	return;
    }

    oaIter<oaModModuleInstHeader>   ihdrIter(top->getModuleInstHeaders());

    while (oaModModuleInstHeader *ihdr = ihdrIter.getNext()) {
        oaModule    *master = ihdr->getMasterModule();
        
        if (!master) {
	    unboundInstHeader(ihdr);
            continue;
        }
        
	walkModuleHier(master);
    }

    if (options.testProduceLeaf()) {
	oaIter<oaModInstHeader>	ihdrIter(top->getDesign()->getModInstHeaders());

	while (oaModInstHeader	*ihdr = ihdrIter.getNext()) {
	    if (ihdr->getInsts(oacInstIterNotImplicit, top).isEmpty()) {
		continue;
	    }

	    oaModule	*master = ihdr->getMasterModule();

	    if (!master) {
		unboundInstHeader(ihdr);
		continue;
	    }

	    writeLeaf(*master);
	}
    }

    writeCell(*top);
    printedModule->set(top, Printed);
}



// *****************************************************************************
// VerilogOut::writeCell()
//
// This function triggers the CallbacksOut to write a module.
// *****************************************************************************
void
VerilogOut::writeCell(oaModule	&cell)
{
    verilogCB->writeCell(cell);
}



// *****************************************************************************
// VerilogOut::writeLeaf()
//
// This function triggers the CallbacksOut to write a leaf module. A 
// leaf module is a module that exists in a design other that the design that 
// contains the top module.
// *****************************************************************************
void
VerilogOut::writeLeaf(oaModule	&cell)
{
    if (printedModule->get(&cell) == Printed) {
	return;
    }

    printedModule->set(&cell, Printed);

    leafCB->writeCell(cell);
}



// *****************************************************************************
// VerilogOut::unboundInstHeader()
//
// These functions are called when unbound inst headers are encountered.  They
// display a warning message that the master module for the header will not be
// produced.
// *****************************************************************************
void
VerilogOut::unboundInstHeader(oaModInstHeader	*ihdr)
{
    oaString	libName;
    oaString	cellName;
    oaString	viewName;

    ihdr->getLibName(vns, libName);
    ihdr->getCellName(vns, cellName);
    ihdr->getViewName(vns, viewName);

    Error  msg(NoModule, NULL, (const char*) (libName + "." + cellName + "." 
	       + viewName));

    options.getMsgAdapter()->printWarning("%s\n", (const char*) msg.getMsg());
}

void
VerilogOut::unboundInstHeader(oaModModuleInstHeader *ihdr)
{
    oaString	name;

    ihdr->getName(vns, name);

    Error  msg(NoModule, NULL, (const char*) name);

    options.getMsgAdapter()->printWarning("%s\n", (const char*) msg.getMsg());
}



END_VERILOG_NAMESPACE