oaverilogmsgs.eng

openaccess与verilog互相转化时所用的源代码

// *****************************************************************************
// *****************************************************************************
// oaVerilogMsgs.eng
//
// This files contains the English messages used by oaVerilog exceptions.
// Note that the order of the message text defined in this file must match 
// the order of the message identifiers declared in the file Msgs.h.
//
// *****************************************************************************
// Except as specified in the OpenAccess terms of use of Cadence or Silicon
// Integration Initiative, this material may not be copied, modified,
// re-published, uploaded, executed, or distributed in any way, in any medium,
// in whole or in part, without prior written permission from Cadence.
//
//                Copyright 2002-2005 Cadence Design Systems, Inc.
//                           All Rights Reserved.
//
//  $Author: shaun $
//  $Revision: 1.38 $
//  $Date: 2005/07/12 15:57:11 $
//  $State: Exp $
// *****************************************************************************
// *****************************************************************************



#ifndef oaVerilogMsgs_eng_P
#define oaVerilogMsgs_eng_P

BEGIN_VERILOG_NAMESPACE






// *****************************************************************************
// Messages
// *****************************************************************************
const oaString  Msgs[] = {
    "%s",
    "Unable to open file \"%s\"",
    "Syntax Error: %s",
    "Module \"%s\" is not the top module of design \"%s\"",
    "Always blocks are not implemented",
    "Binary operators are not implemented",
    "Config declarations are not implemented",
    "At least one element of a concatentation must be a string",
    "Event declarations are not implemented",
    "Function calls are not implemented",
    "Function declarations are not implemented",
    "Gate instantiations are not implemented",
    "Generate blocks are not implemented",
    "Genvar declarations are not implemented",
    "Include statements are not implemented",
    "Initial statements are not implemented",
    "The width of net \"%s\" is not equal to the width of term \"%s\" times the width of instance \"%s\"",
    "Integer arrays are not implemented",
    "\"%s\" is not a valid instance name",
    "Library text is not implemented",
    "min:typ:max expressions always evaluate to \"typ\"",
    "Multi-dimensional nets are not implemented",
    "Multi-dimensional objects are not implemented",
    "Multi-dimensional registers are not implemented",
    "Negative values in ranges are not allowed",
    "The IEEE 1364-2001 standard specifies that the expression following an \"if\" or \"while\" statement must be enclosed in parentheses",
    "The size field of a number must be greater than zero",
    "The specified number of bits is larger than the number of bits in an unsigned integer",
    "\"x\" digits are not implemented",
    "\"z\" digits are not implemented",
    "Primitives are not implemented",
    "Real declarations are not implemented",
    "Realtime declarations are not implemented",
    "Specparam statements are not implemented",
    "Tasks are not implemented",
    "Terminal \"%s\" was not found in module \"%s\"",
    "Terminal at position %d in \"%s.%s.%s\" was not found",
    "Time declarations are not implemented",
    "User defined primitives are not implemented",
    "Unary operators are not implemented",
    "The width of terminal \"%s\" must be greater than or equal to the width of net \"%s\"",
    "Parameter arrays not implemented",
    "Hierarchical names must be of the form \"module\".\"net\"",
    "Module \"%s\" is not the module that contains global nets",
    "Library \"%s\" was not found\n",
    "Unresolved references exist for the following modules: %s",
    "Terminal \"%s\" of module \"%s\" has position %d but the Verilog specification places it at position %d",
    "The direction of terminal \"%s\" is not declared consistently",
    "Inconsistent width specified for terminal \"%s\" of module \"%s\"",
    "Inconsistent bit order for \"%s\"",
    "Local declaration of the global net used for 1'b1 references, \"%s\"",
    "Local declaration of the global net used for 1'b0 references, \"%s\"",
    "The specified top module \"%s\" was not defined in the Verilog input",
    "No master module for instances of \"%s\" the module will not be produced",
    "Inconsistent width specified for terminal at position %d of module \"%s\"",
    "Cell \"%s\" was not found in any library",
    "Verilog module \"%s\" is represented by the top module of %s.%s.%s, \"%s\"",
    "Design %s.%s.%s does not have a top module",
    "Design %s.%s.%s exists. Cannot overwrite existing design data by default",
    "Library %s was not found",
    "\"%s\" is not a valid library name: %s",
    "\"%s\" is not a valid view name: %s",
    "Cannot convert string \"%s\" to a binary number",
    "Cannot convert floating point number \"%s\" to a binary number",
    "No design instance with the name \"%s\" was found",
    "The width of terminal \"%s\" does not match the width of net \"%s\". Some bits are unconnected.",
    "The width of terminal \"%s\" does not match the width of net \"%s\".",
    "The directions of the members of \"%s\" are not consistent",
    "Undefined message ID"
};



END_VERILOG_NAMESPACE

#endif