gnumakefile

openaccess与verilog互相转化时所用的源代码

# ******************************************************************************
# ******************************************************************************
# This makefile contains the rules for building the oaVerilog library.
#
# ******************************************************************************
# Except as specified in the OpenAccess terms of use of Cadence or Silicon
# Integration Initiative, this material may not be copied, modified,
# re-published, uploaded, executed, or distributed in any way, in any medium,
# in whole or in part, without prior written permission from Cadence.
#
#                Copyright 2002-2005 Cadence Design Systems, Inc.
#                           All Rights Reserved.
#
#  $Author: ghijsen $
#  $Revision: 1.10 $
#  $Date: 2005/03/29 00:08:56 $
# ******************************************************************************
# ******************************************************************************


ROOT		= ..

include $(ROOT)/build.variables

default : all

PROJ_INCLUDES	:= -I$(TOOL_INCLUDE_DIR)	\
		   -I$(PROD_DIR)/include/oa	\
		   -I$(OBJDIR)
PROJ_NAME	= oaVerilog

include Hfiles.defs


# ******************************************************************************
# Define the archive library
# ******************************************************************************
LIB_NAME	:= lib$(PROJ_NAME)
LIB_RULE	:= $(PROJ_NAME)_so
LIB_MODE	:= archive
LIB_LANG	:= C++
LIB_PIC		:= yes
LIB_PREGEN_SRC  := oaVerilogParser.hpp oaVerilogParser.cpp oaVerilogScanner.cpp
LIB_INST_HDRS	:= $(HFILES)
LIB_INST_HDRSDIR:= $(TOOL_INCLUDE_DIR)
LIB_SRC		:= $(wildcard *.cpp)
LIB_INST_BINDIR	:= $(PROD_LIB_DIR)

include $(CONFIG_ROOT)/library.rules

include $(ROOT)/build.rules

# Default values for FLEX_HOME and BISON_HOME are defined in local.rules
LEX    	        := $(FLEX_HOME)/bin/flex++
LFILE           := oaVerilogScanner.lpp
LFLAGS          := -t -PvliYY -SoaVerilogScanner.skl

YACC   	        := $(BISON_HOME)/bin/bison
YFILE           := oaVerilogParser.ypp
YFLAGS          := --skeleton=oaVerilogParser.skl \
		   --name-prefix=Parser \
		   --defines \
		   --file-prefix=oaVerilogParser \
		   --report=itemset \
		   --verbose \
		   --output=oaVerilogParser.cpp

BISON_PKGDATADIR  = $(shell pwd)
BISON_OUTPUT	 := oaVerilogParser.cpp \
		    oaVerilogParser.hpp \
		    location.hh         \
		    position.hh         \
		    stack.hh

define generate-parser
    $(SECHO) "Generating parser with $(YACC) $<"
    $(WHISPER) csh -c 					\
	"cd $(OBJDIR);					\
	ln -s $(BISON_PKGDATADIR)/$(YFILE) $(YFILE);	\
	setenv BISON_PKGDATADIR $(BISON_PKGDATADIR);	\
	$(YACC) $(YFLAGS) $(YFILE);"
endef

define generate-scanner
    $(SECHO) "Generating scanner with $(LEX) $<"
    $(WHISPER) $(LEX) $(LFLAGS) $(LFILE) > $@
endef

$(OBJDIR)/oaVerilogScanner.cpp:	$(LFILE) $(OBJDIR)/oaVerilogParser.hpp oaVerilogScanner.skl
	$(generate-scanner)

$(OBJDIR)/oaVerilogParser.cpp: 	$(YFILE) oaVerilogParser.skl
	$(generate-parser)

$(OBJDIR)/oaVerilogParser.hpp: 	$(YFILE) oaVerilogParser.skl
	$(generate-parser)