excep_s.s

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/************************************************************************
 *
 *  excep_s.S
 *
 *  First level exception handling functions.
 *
 * ######################################################################
 *
 * mips_start_of_legal_notice
 * 
 * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved.
 *
 *
 * Unpublished rights (if any) reserved under the copyright laws of the
 * United States of America and other countries.
 *
 * This code is proprietary to MIPS Technologies, Inc. ("MIPS
 * Technologies"). Any copying, reproducing, modifying or use of this code
 * (in whole or in part) that is not expressly permitted in writing by MIPS
 * Technologies or an authorized third party is strictly prohibited. At a
 * minimum, this code is protected under unfair competition and copyright
 * laws. Violations thereof may result in criminal penalties and fines.
 *
 * MIPS Technologies reserves the right to change this code to improve
 * function, design or otherwise. MIPS Technologies does not assume any
 * liability arising out of the application or use of this code, or of any
 * error or omission in such code. Any warranties, whether express,
 * statutory, implied or otherwise, including but not limited to the implied
 * warranties of merchantability or fitness for a particular purpose, are
 * excluded. Except as expressly provided in any written license agreement
 * from MIPS Technologies or an authorized third party, the furnishing of
 * this code does not give recipient any license to any intellectual
 * property rights, including any patent rights, that cover this code.
 *
 * This code shall not be exported, reexported, transferred, or released,
 * directly or indirectly, in violation of the law of any country or
 * international law, regulation, treaty, Executive Order, statute,
 * amendments or supplements thereto. Should a conflict arise regarding the
 * export, reexport, transfer, or release of this code, the laws of the
 * United States of America shall be the governing law.
 *
 * This code constitutes one or more of the following: commercial computer
 * software, commercial computer software documentation or other commercial
 * items. If the user of this code, or any related documentation of any
 * kind, including related technical data or manuals, is an agency,
 * department, or other entity of the United States government
 * ("Government"), the use, duplication, reproduction, release,
 * modification, disclosure, or transfer of this code, or any related
 * documentation of any kind, is restricted in accordance with Federal
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use
 * of this code by the Government is further restricted in accordance with
 * the terms of the license agreement(s) and/or applicable contract terms
 * and conditions covering this code from MIPS Technologies or an authorized
 * third party.
 *
 *
 *
 * 
 * mips_end_of_legal_notice
 * 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <mips.h>
#include <gdb_stub.h>
#include <sys_api.h>	
#include <product.h>	
#include <malta.h>	
	
/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public and static variables
 ************************************************************************/

	BSS
	
	/* 32 bit align */
	ALIGN(2)
	
	.globl EXCEP_shell_sp
EXCEP_shell_sp:
	.space	4

exc_handler_args:
	.space  8

ejtag_handler_arg:
	.space  4

excep_cp0_regs_mask:
	.space	4

excep_tmp:
	.space  4
	
exc_stack_low:
	.space  SYS_STACK_SIZE

	ALIGN(4) /* 16 bytes align */
exc_context:
	.space	EXCEP_SIZE_CONTEXT


ejtag_stack_low:
	.space  SYS_STACK_SIZE >> 4

	ALIGN(4) /* 16 bytes align */

	.globl ejtag_context
ejtag_context:
	.space	EXCEP_SIZE_CONTEXT


/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

	.set noat
	.set noreorder
	
	.globl EXCEP_return
	
/************************************************************************
 *
 *                          fpuemul_putchar
 *  Description :
 *  -------------
 *
 *  This routine is called from fpu exception only.
 *  It sets up the minimum yamon context (gp) and calls sys_putchar.
 *  All registers except sp, gp, s0-s8, k0-k1  may be destroyed.
 *
 *  Parameters :
 *  ------------
 *
 *  a0 = char to be written
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( fpuemul_putchar )
	/* make room (must be 16 byte aligned) and save minimal context */
	addiu	sp, -8*4
	sw	gp, 16(sp)
	sw	ra, 20(sp)

	/* set up yamon minimal context */
	move	a1, a0
	jal	sys_putchar
	li	a0, DEFAULT_PORT
	
	/* restore minimal context */
	lw	ra, 20(sp)
	lw	gp, 16(sp)
	jr	ra
	addiu	sp, 8*4
END( fpuemul_putchar )


/************************************************************************
 *
 *                          EXCEP_init_reg_mask
 *  Description :
 *  -------------
 *  Determine what CP0/CP1 regs should be context switched.
 *
 *  Parameters :
 *  ------------
 *
 *  Return values :
 *  ---------------
 *  None
 *
 ************************************************************************/
LEAF( EXCEP_init_reg_mask )

    /* Determine availability of regs :
     *
     * Bit 0 = 32(1) or 64(0) bit CPU
     * Bit 1 = FPU
     * Bit 2 = TLB
     * Bit 3 = Watch registers
     * Bit 4 = MIPS32/MIPS64
     * ----- Following only apply to MIPS32/MIPS64
     * Bit 5 = EJTAG (MIPS32/64 only)
     * Bit 6 = MIPS32/MIPS64 Release 2
     * Bit 7 = SRSMap
     * Bit 8 = PageGrain
     */

    /* Check for 32 or 64 bit CPU */
    la		t0, sys_64bit
    lb		t0, 0(t0)
    bne		t0, zero, 1f
    move	t0, zero
    ori		t0, 0x1
1:
    /* Check for FPU */
    la		t1, sys_fpu
    lw		t1, 0(t1)
    beq		t1, zero, 1f
    nop
    ori		t0, 0x2
1:
    /* Check for MIPS32/MIPS64 */
    la		t1, sys_mips32_64
    lw		t1, 0(t1)
    bne		t1, zero, 1f
    nop
    b		non_mips32_64
    ori		t0, 0x4+0x8  /* Assume TLB + Watch for non MIPS32/MIPS64 */
1:
    ori		t0, 0x10

    /* Check for TLB based on Config.MT */
    MFC0_SEL_OPCODE( R_t1, R_C0_Config, R_C0_SelConfig )
    li		t2, M_ConfigMT
    and		t2, t1
    srl		t2, S_ConfigMT
    li		t3, K_ConfigMT_TLBMMU
    bne		t2, t3, 1f
    nop
    ori		t0, 0x4
1:
    /* Determine Release 2 based on Config.AR */
    li		t2, M_ConfigAR
    and		t1, t2
    srl		t1, S_ConfigAR
    beq		t1, zero, non_release2
    nop
    ori		t0, 0x40

    /* Determine SRSMap (Release 2 only) based on SRSCtl.HSS and Config3.VInt */
    MFC0_SEL_OPCODE( R_t1, R_C0_SRSCtl, R_C0_SelSRSCtl )
    li		t2, M_SRSCtlHSS
    and		t1, t2
    beq		t1, zero, 1f
    nop
    MFC0_SEL_OPCODE( R_t1, R_C0_Config3, R_C0_SelConfig3 ) /* Since HSS!=0, Config3 is required */
    sll		t1, 31-S_Config3VInt
    bgez	t1, 1f
    nop
    ori		t0, 0x80
1:
    /* Determine PageGrain (Release 2 only) based on :
     *
     *   Config3.LPA (large physical addresses) 
     *   Config3.SP  (small page support)
     *
     *   TBD : SmartMIPS
     */
    MFC0_SEL_OPCODE( R_t1, R_C0_Config1, R_C0_SelConfig1 )
    sll		t1, 31-S_ConfigMore
    bgez	t1, 1f
    nop
    MFC0_SEL_OPCODE( R_t1, R_C0_Config2, R_C0_SelConfig2 )
    sll		t1, 31-S_ConfigMore
    bgez	t1, 1f
    nop
    MFC0_SEL_OPCODE( R_t1, R_C0_Config3, R_C0_SelConfig3 )
    li		t2, M_Config3LPA | M_Config3SP
    and		t1, t2
    beq		t1, zero, 1f
    nop
    ori		t0, 0x100
1:	
non_release2:
    /* Determine Watch registers based on Config1.WR */
    MFC0_SEL_OPCODE( R_t1, R_C0_Config1, R_C0_SelConfig1 )
    sll		t2, t1, 31-S_Config1WR
    bgez	t2, 1f
    nop
    ori		t0, 0x8
1:
    /* Determine EJTAG regs based on Config1.EP */
    sll		t1, 31-S_Config1EP
    bgez	t1, 1f
    nop
    ori		t0, 0x20
1:
non_mips32_64:
    /* Done. Store result and return */
    la		t1, excep_cp0_regs_mask
    jr 		ra
    sw		t0, 0(t1)

END( EXCEP_init_reg_mask )

		
/************************************************************************
 *
 *                          EXCEP_install_exc_in_ram
 *  Description :
 *  -------------
 *  Install jump instructions to exc handler at exception vector locations
 *
 *  Parameters :
 *  ------------
 *
 *  Return values :
 *  ---------------
 *  None
 *
 ************************************************************************/
LEAF( EXCEP_install_exc_in_ram )

	/* Install RAM exception vectors */

#define ADDR			a0  /* also used as arg to sys_cache..() */
#define STATUS_INT		t3
#define RA			t4
	
	move	RA, ra

	/* Disable interrupts */
	MFC0(   t1, C0_Status )
	and	STATUS_INT, t1, M_StatusIE
	xor	t1,	    STATUS_INT	
	MTC0(   t1,	    C0_Status )
	
	/**** install yamon ram vectors ****/
	jal	setup_yamon_vector
	li	ADDR, 0x0	/* TLB refill     */

	jal	setup_yamon_vector
	li	ADDR, 0x80	/* XTLB refill    */

	la	t2, ram_vector_cacheerr
	jal	setup_yamon_vector_cacheerr
	li	ADDR, 0x100     /* Cache error    */
	
	la	t2, ram_vector_general
	jal	setup_yamon_vector_general
	li	ADDR, 0x180	/* General        */

	jal	setup_yamon_vector
	li	ADDR, 0x200	/* Int, CauseIV=1 */	

	jal	setup_yamon_vector_ejtag
	li	ADDR, SYS_EJTAG_RAM_VECTOR_OFS

	jal	setup_yamon_vector
	li	ADDR, SYS_NMI_RAM_VECTOR_OFS

	
	/* Clear BEV so that ram handlers are used */
	MFC0(   a0, C0_Status)
	li	t2, ~M_StatusBEV
	and	a0, t2
	MTC0(   a0, C0_Status)

	/* Restore interrupt enable state */
	or	a0, STATUS_INT
	MTC0(   a0, C0_Status )

	move	ra, RA

	/* Done */
	jr	ra
	nop

	
setup_yamon_vector_ejtag:
	la	t2, ram_vector_ejtag	

	/* Save existing data of exception vector location */
	/* Copy ram vector code to exception vector location */

	li	t1, KSEG0BASE
	or	ADDR, t1		/* Destination   */

	/* Install new yamon vector    */
	lw	t1, 0(t2)
	sw	t1, 0(ADDR)
	lw	t1, 4(t2)
	sw	t1, 4(ADDR)

	b	cache_flush_vector
	nop

setup_yamon_vector:
	la	t2, ram_vector_normal

setup_yamon_vector_cacheerr:
setup_yamon_vector_general:
	/* Save existing data of exception vector location */
	/* Copy ram vector code to exception vector location */

	li	t1, KSEG0BASE
	or	ADDR, t1		/* Destination   */

	/* Install new yamon vector    */
	lw	t1, 0(t2)
	sw	t1, 0(ADDR)
	lw	t1, 4(t2)		/* li k1, 0x0000  */
	and	t2, ADDR, 0xffff
	or	t1, t2			/* li k1, vector_offset */
	sw	t1, 4(ADDR)


cache_flush_vector:

	/* Whenever an instruction has been stored to KSEG0, we must
	 * make sure the instruction has been flushed to physical memory
	 * and invalidate the corresponding I-Cache line.
	 *     sys_dcache_flush_addr modifies only t1.
	 *     sys_icache_invalidate_addr modifies only t1.
	 */

	move	t2, ra

	jal     sys_dcache_flush_addr
	nop
	jal	sys_icache_invalidate_addr
	move	a1, zero /* No need to flush pipeline */
			
	jr	t2
	nop

END( EXCEP_install_exc_in_ram )	


SLEAF( EXCEP_yamon_ram_vectors )
	
ram_vector_normal:
	/*  This code is copied to the various ram exception vector
	 *  locations (2 words are copied).
	 */
	j	exc_handler
	li	k0, 0		/* when copied: "li k0, vector_offset" */

ram_vector_cacheerr:
	/*  This code is copied to the cacheerr exception ram vector
	 *  location (2 words are copied).
	 */
	j	exc_handler_cacheerr
	li	k0, 0		/* when copied: "li k0, vector_offset" */

ram_vector_general:
	/*  This code is copied to the general exception ram vector
	 *  location (2 words are copied).
	 */
	j	exc_handler_general
	li	k0, 0		/* when copied: "li k0, vector_offset" */

ram_vector_ejtag:
	/*  This code is copied to the exception vector
	 *  location reserved (by YAMON) for EJTAG (i.e. 0x80000300)
	 *  (2 words are copied).
	 *  This entry is software redirected from addr 0xbf000480.
	 *  Please see the file reset.S for a note about hazards.
	 */
	j	exc_handler_ejtag
        mtc0    k1, C0_DESAVE
	
END( EXCEP_yamon_ram_vectors )


SLEAF( EXCEP_yamon_vector_handler )
/*********************************************************************
**      Special ejtag exception entry
*/
exc_handler_ejtag:

	/**** Store k0 (k1 has been stored in CP0) ****/
	/* Store sp and k1 in readable exception context */
	la	k1,   sys_64bit
	lb	k1,   0(k1)
	bne	k1,   zero, 64f
	nop

	la	k1,   ejtag_context
	sw	k0,   GDB_REG32_OFS(GDB_FR_REG26)(k1)
        mfc0    k0,   C0_DESAVE
	sw	k0,   GDB_REG32_OFS(GDB_FR_REG27)(k1)
	b	2f
	sw	$31,  GDB_REG32_OFS(GDB_FR_REG31)(k1)

64:
	la	k1,   ejtag_context
SET_MIPS3()
        sd	k0,   GDB_REG64_OFS(GDB_FR_REG26)(k1)
        mfc0    k0,   C0_DESAVE
        sd	k0,   GDB_REG64_OFS(GDB_FR_REG27)(k1)
        sd	$31,  GDB_REG64_OFS(GDB_FR_REG31)(k1)
SET_MIPS0()
2:

	/**** Store context ****/
	jal	EXCEP_store_gpr_but_k0k1ra
	nop
	jal	store_cp1_gpr_cp0_control
	nop

	/* Set up arguments for exception_ejtag() */
	la	a0, ejtag_handler_arg
	li	a1, 0
1:
	sw	a1, 0(a0)
	move	a0, k1

	/* call low level exception handler */

	jal	exception_ejtag /* It is imperative that k1 survives */