excep_s.s

来自「MIPS YAMON, a famous monitor inc. source」· S 代码 · 共 2,069 行 · 第 1/4 页

		
    MFC0(	t1, C0_EntryLo1 )
    sw		t1, GDB_REG32_OFS(GDB_FR_CP0_ENTRYLO1)(a0)

    MFC0(	t1, C0_Context )
    sw		t1, GDB_REG32_OFS(GDB_FR_CP0_CONTEXT)(a0)

    MFC0(	t1, C0_PageMask )
    sw		t1, GDB_REG32_OFS(GDB_FR_CP0_PAGEMASK)(a0)

    MFC0(	t1, C0_Wired )
    sw		t1, GDB_REG32_OFS(GDB_FR_CP0_WIRED)(a0)

    MFC0(	t1, C0_EntryHi )
    sw		t1, GDB_REG32_OFS(GDB_FR_CP0_ENTRYHI)(a0)
1:
    /* Check for Watch registers */
    sll		t1, t0, 31-3
    bgez	t1, 1f
    nop

    /* Watch registers */
    MFC0(       t1, C0_WatchLo )
    sw	        t1, GDB_REG32_OFS(GDB_FR_CP0_WATCHLO)(a0)

    MFC0(       t1, C0_WatchHi )
    sw	        t1, GDB_REG32_OFS(GDB_FR_CP0_WATCHHI)(a0)
1:
    /* Check for MIPS32/MIPS64 */
    sll		t1, t0, 31-4
    bgez	t1, 1f
    nop

    /* MIPS32/MIPS64 */
    
    /* Config1 (required for MIPS32/MIPS64 CPUs) */
    MFC0_SEL_OPCODE( R_t1, R_C0_Config1, R_C0_SelConfig1 )
    sw	        t1, GDB_REG32_OFS(GDB_FR_CP0_CONFIG1)(a0)

    /* Config2 depends on M bit of Config1 */
    sll		t1, 31-S_ConfigMore
    bgez	t1, 2f
    nop
    MFC0_SEL_OPCODE( R_t1, R_C0_Config2, R_C0_SelConfig2 )
    sw	        t1, GDB_REG32_OFS(GDB_FR_CP0_CONFIG2)(a0)

    /* Config3 depends on M bit of Config2 */
    sll		t1, 31-S_ConfigMore
    bgez	t1, 2f
    nop
    MFC0_SEL_OPCODE( R_t1, R_C0_Config3, R_C0_SelConfig3 )
    sw	        t1, GDB_REG32_OFS(GDB_FR_CP0_CONFIG3)(a0)
2:
    /* Check for EJTAG */
    sll		t1, t0, 31-5
    bgez	t1, 2f
    nop

    /* EJTAG regs */
    MFC0(	t1, C0_Debug )
    sw		t1, GDB_REG32_OFS(GDB_FR_CP0_DEBUG)(a0)

    MFC0(	t1, C0_DEPC )
    sw		t1, GDB_REG32_OFS(GDB_FR_CP0_DEPC)(a0)
2:
    /* Check for Release 2 */
    sll		t1, t0, 31-6
    bgez	t1, 2f
    nop

    /* Release 2 */
    MFC0(       t1, C0_HWREna )
    sw		t1, GDB_REG32_OFS(GDB_FR_CP0_HWRENA)(a0)

    MFC0_SEL_OPCODE( R_t1, R_C0_IntCtl, R_C0_SelIntCtl )
    sw		t1, GDB_REG32_OFS(GDB_FR_CP0_INTCTL)(a0)

    MFC0_SEL_OPCODE( R_t1, R_C0_SRSCtl, R_C0_SelSRSCtl )
    sw	        t1, GDB_REG32_OFS(GDB_FR_CP0_SRSCTL)(a0)

    MFC0_SEL_OPCODE( R_t1, R_C0_EBase, R_C0_SelEBase )
    sw	        t1, GDB_REG32_OFS(GDB_FR_CP0_EBASE)(a0)

    /* SRSMap */
    sll		t1, t0, 31-7
    bgez	t1, 2f
    nop

    MFC0_SEL_OPCODE( R_t1, R_C0_SRSMap, R_C0_SelSRSMap )
    sw	        t1, GDB_REG32_OFS(GDB_FR_CP0_SRSMAP)(a0)
2:
    /* PageGrain */
    sll		t1, t0, 31-8
    bgez	t1, 1f
    nop

    MFC0_SEL_OPCODE( R_t1, R_C0_PageGrain, R_C0_SelPageGrain )
    sw	        t1, GDB_REG32_OFS(GDB_FR_CP0_PAGEGRAIN)(a0)
1:
    /* Done */
    jr ra
    nop

store_control_64bit :

SET_MIPS3()
	
    /* Status register (always available) */
    MFC0(       t1, C0_Status)
    sd		t1, GDB_REG64_OFS(GDB_FR_STATUS)(a0)
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_REG12)(a0)

    /* Check for FPU */
    sll		t2, t0, 31-1
    bgez	t2, 1f
    nop
    /* Check that FPU is enabled */
    sll		t1, 31-S_StatusCU1
    bgez	t1, 1f
    nop

    /* Store FPU registers */
    cfc1        t1, $0
    cfc1	t2, $31
    sd		t1, GDB_REG64_OFS(GDB_FR_FIR)(a0)
    sd		t2, GDB_REG64_OFS(GDB_FR_FSR)(a0)
1:
    /* Registers available for all MIPS CPUs */
    mflo	t1
    sd		t1, GDB_REG64_OFS(GDB_FR_LO)(a0)

    mfhi	t1
    sd		t1, GDB_REG64_OFS(GDB_FR_HI)(a0)		

    DMFC0(      t1, C0_BadVAddr )
    sd		t1, GDB_REG64_OFS(GDB_FR_BADVADDR)(a0)
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_REG8)(a0)	

    MFC0(	t1, C0_Count )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_REG9)(a0)

    MFC0(	t1, C0_Compare )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_REG11)(a0)

    MFC0(	t1, C0_Cause )
    sd		t1, GDB_REG64_OFS(GDB_FR_CAUSE)(a0)
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_REG13)(a0)

    DMFC0(	t1, C0_EPC )
    sd		t1, GDB_REG64_OFS(GDB_FR_EPC)(a0)
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_REG14)(a0)

    MFC0(	t1, C0_PRId )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_PRID)(a0)

    DMFC0(	t1, C0_ErrorEPC )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_ERROREPC)(a0)

    MFC0_SEL_OPCODE( R_t1, R_C0_Config, R_C0_SelConfig )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_CONFIG)(a0)

    /* Check for TLB */
    sll		t1, t0, 31-2
    bgez	t1, 1f
    nop

    /* TLB */
    MFC0(       t1, C0_Index )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_INDEX)(a0)

    MFC0(	t1, C0_Random )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_RANDOM)(a0)

    DMFC0(	t1, C0_EntryLo0 )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_ENTRYLO0)(a0)
		
    DMFC0(	t1, C0_EntryLo1 )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_ENTRYLO1)(a0)

    DMFC0(	t1, C0_Context )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_CONTEXT)(a0)

    MFC0(	t1, C0_PageMask )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_PAGEMASK)(a0)

    MFC0(	t1, C0_Wired )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_WIRED)(a0)

    DMFC0(	t1, C0_EntryHi )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_ENTRYHI)(a0)
1:
    /* Check for Watch registers */
    sll		t1, t0, 31-3
    bgez	t1, 1f
    nop

    /* Watch registers */
    DMFC0(      t1, C0_WatchLo )
    sd	        t1, GDB_REG64_OFS(GDB_FR_CP0_WATCHLO)(a0)

    DMFC0(      t1, C0_WatchHi )
    sd	        t1, GDB_REG64_OFS(GDB_FR_CP0_WATCHHI)(a0)
1:
    /* Check for MIPS32/MIPS64 */
    sll		t1, t0, 31-4
    bgez	t1, 1f
    nop

    /* MIPS32/MIPS64 */
    
    /* Config1 (required for MIPS32/MIPS64 CPUs) */
    MFC0_SEL_OPCODE( R_t1, R_C0_Config1, R_C0_SelConfig1 )
    sd	        t1, GDB_REG64_OFS(GDB_FR_CP0_CONFIG1)(a0)

    /* Config2 depends on M bit of Config1 */
    sll		t1, 31-S_ConfigMore
    bgez	t1, 2f
    nop
    MFC0_SEL_OPCODE( R_t1, R_C0_Config2, R_C0_SelConfig2 )
    sd	        t1, GDB_REG64_OFS(GDB_FR_CP0_CONFIG2)(a0)

    /* Config3 depends on M bit of Config2 */
    sll		t1, 31-S_ConfigMore
    bgez	t1, 2f
    nop
    MFC0_SEL_OPCODE( R_t1, R_C0_Config3, R_C0_SelConfig3 )
    sd	        t1, GDB_REG64_OFS(GDB_FR_CP0_CONFIG3)(a0)
2:
    /* Check for EJTAG */
    sll		t1, t0, 31-5
    bgez	t1, 2f
    nop

    /* EJTAG regs */
    MFC0(	t1, C0_Debug )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_DEBUG)(a0)

    DMFC0(	t1, C0_DEPC )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_DEPC)(a0)
2:
    /* Check for Release 2 */
    sll		t1, t0, 31-6
    bgez	t1, 2f
    nop

    /* Release 2 */
    MFC0(       t1, C0_HWREna )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_HWRENA)(a0)

    MFC0_SEL_OPCODE( R_t1, R_C0_IntCtl, R_C0_SelIntCtl )
    sd		t1, GDB_REG64_OFS(GDB_FR_CP0_INTCTL)(a0)

    MFC0_SEL_OPCODE( R_t1, R_C0_SRSCtl, R_C0_SelSRSCtl )
    sd	        t1, GDB_REG64_OFS(GDB_FR_CP0_SRSCTL)(a0)

    MFC0_SEL_OPCODE( R_t1, R_C0_EBase, R_C0_SelEBase )
    sd	        t1, GDB_REG64_OFS(GDB_FR_CP0_EBASE)(a0)

    /* SRSMap */
    sll		t1, t0, 31-7
    bgez	t1, 2f
    nop

    MFC0_SEL_OPCODE( R_t1, R_C0_SRSMap, R_C0_SelSRSMap )
    sd	        t1, GDB_REG64_OFS(GDB_FR_CP0_SRSMAP)(a0)
2:
    /* PageGrain */
    sll		t1, t0, 31-8
    bgez	t1, 1f
    nop

    MFC0_SEL_OPCODE( R_t1, R_C0_PageGrain, R_C0_SelPageGrain )
    sd	        t1, GDB_REG64_OFS(GDB_FR_CP0_PAGEGRAIN)(a0)
1:

SET_MIPS0()
	
    /* Done */	
    jr ra
    nop
	
END( sys_store_control_regs )

	

LEAF( EXCEP_restore_gpr_but_k1 )

        /* k0 points to context, k1 = return address */

	la	t6, sys_64bit
	lb	t6, 0(t6)
	bne	t6, zero, 64f
	nop

	/* Restore 32 bit CPU register bank */	
	lw	$0,   GDB_REG32_OFS(GDB_FR_REG0 )(k0)
	lw	$1,   GDB_REG32_OFS(GDB_FR_REG1 )(k0)
	lw	$2,   GDB_REG32_OFS(GDB_FR_REG2 )(k0)
	lw	$3,   GDB_REG32_OFS(GDB_FR_REG3 )(k0)
	lw	$4,   GDB_REG32_OFS(GDB_FR_REG4 )(k0)
	lw	$5,   GDB_REG32_OFS(GDB_FR_REG5 )(k0)
	lw	$6,   GDB_REG32_OFS(GDB_FR_REG6 )(k0)
	lw	$7,   GDB_REG32_OFS(GDB_FR_REG7 )(k0)
	lw	$8,   GDB_REG32_OFS(GDB_FR_REG8 )(k0)
	lw	$9,   GDB_REG32_OFS(GDB_FR_REG9 )(k0)
	lw	$10,  GDB_REG32_OFS(GDB_FR_REG10)(k0)
	lw	$11,  GDB_REG32_OFS(GDB_FR_REG11)(k0)
	lw	$12,  GDB_REG32_OFS(GDB_FR_REG12)(k0)
	lw	$13,  GDB_REG32_OFS(GDB_FR_REG13)(k0)
	lw	$14,  GDB_REG32_OFS(GDB_FR_REG14)(k0)
	lw	$15,  GDB_REG32_OFS(GDB_FR_REG15)(k0)
	lw	$16,  GDB_REG32_OFS(GDB_FR_REG16)(k0)
	lw	$17,  GDB_REG32_OFS(GDB_FR_REG17)(k0)
	lw	$18,  GDB_REG32_OFS(GDB_FR_REG18)(k0)
	lw	$19,  GDB_REG32_OFS(GDB_FR_REG19)(k0)
	lw	$20,  GDB_REG32_OFS(GDB_FR_REG20)(k0)
	lw	$21,  GDB_REG32_OFS(GDB_FR_REG21)(k0)
	lw	$22,  GDB_REG32_OFS(GDB_FR_REG22)(k0)
	lw	$23,  GDB_REG32_OFS(GDB_FR_REG23)(k0)
	lw	$24,  GDB_REG32_OFS(GDB_FR_REG24)(k0)
	lw	$25,  GDB_REG32_OFS(GDB_FR_REG25)(k0)
	/* Not k0 and k1 = $26, $27 */	
	lw	$28,  GDB_REG32_OFS(GDB_FR_REG28)(k0)
	lw	$29,  GDB_REG32_OFS(GDB_FR_REG29)(k0)
	lw	$30,  GDB_REG32_OFS(GDB_FR_REG30)(k0)
	lw	$31,  GDB_REG32_OFS(GDB_FR_REG31)(k0)

	jr	k1
	lw	$26,  GDB_REG32_OFS(GDB_FR_REG26)(k0) /* "restore" k0 */
	
64:

SET_MIPS3()
	
	/* Restore 64 bit CPU register bank */	
        ld      $0,  GDB_REG64_OFS(GDB_FR_REG0 )(k0)
        ld      $1,  GDB_REG64_OFS(GDB_FR_REG1 )(k0)
        ld      $2,  GDB_REG64_OFS(GDB_FR_REG2 )(k0)
        ld      $3,  GDB_REG64_OFS(GDB_FR_REG3 )(k0)
        ld      $4,  GDB_REG64_OFS(GDB_FR_REG4 )(k0)
        ld      $5,  GDB_REG64_OFS(GDB_FR_REG5 )(k0)
        ld      $6,  GDB_REG64_OFS(GDB_FR_REG6 )(k0)
        ld      $7,  GDB_REG64_OFS(GDB_FR_REG7 )(k0)
        ld      $8,  GDB_REG64_OFS(GDB_FR_REG8 )(k0)
        ld      $9,  GDB_REG64_OFS(GDB_FR_REG9 )(k0)
        ld      $10, GDB_REG64_OFS(GDB_FR_REG10)(k0)
        ld      $11, GDB_REG64_OFS(GDB_FR_REG11)(k0)
        ld      $12, GDB_REG64_OFS(GDB_FR_REG12)(k0)
        ld      $13, GDB_REG64_OFS(GDB_FR_REG13)(k0)
        ld      $14, GDB_REG64_OFS(GDB_FR_REG14)(k0)
        ld      $15, GDB_REG64_OFS(GDB_FR_REG15)(k0)
        ld      $16, GDB_REG64_OFS(GDB_FR_REG16)(k0)
        ld      $17, GDB_REG64_OFS(GDB_FR_REG17)(k0)
        ld      $18, GDB_REG64_OFS(GDB_FR_REG18)(k0)
        ld      $19, GDB_REG64_OFS(GDB_FR_REG19)(k0)
        ld      $20, GDB_REG64_OFS(GDB_FR_REG20)(k0)
        ld      $21, GDB_REG64_OFS(GDB_FR_REG21)(k0)
        ld      $22, GDB_REG64_OFS(GDB_FR_REG22)(k0)
        ld      $23, GDB_REG64_OFS(GDB_FR_REG23)(k0)
        ld      $24, GDB_REG64_OFS(GDB_FR_REG24)(k0)
        ld      $25, GDB_REG64_OFS(GDB_FR_REG25)(k0)
	/* Not k0, k1 = $26, $27 */
        ld      $28, GDB_REG64_OFS(GDB_FR_REG28)(k0)
        ld      $29, GDB_REG64_OFS(GDB_FR_REG29)(k0)
        ld      $30, GDB_REG64_OFS(GDB_FR_REG30)(k0)
        ld      $31, GDB_REG64_OFS(GDB_FR_REG31)(k0)

	jr	k1
        ld      $26, GDB_REG64_OFS(GDB_FR_REG26)(k0) /* "restore" k0 */

SET_MIPS0()

END( EXCEP_restore_gpr_but_k1 )

	
/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/

	
SLEAF(store_cp1_gpr_cp0_control)

	la	t1, sys_fpu
	lw	t1, 0(t1)
	beq	t1, zero, store_control
	nop

	MFC0(   t1, C0_Status)
	sll	t0, t1, 31-S_StatusCU1
	bgez	t0, store_control
	sll	t0, t1, 31-S_StatusFR
	bgez	t0, store_fpu_gpr_32bit
	nop

	/* Store 64 bit FPU registers */	
	SDC1(   R_fp0,   R_k1, GDB_REG64_OFS(GDB_FR_FPR0 ) )
	SDC1(   R_fp1,   R_k1, GDB_REG64_OFS(GDB_FR_FPR1 ) )
	SDC1(   R_fp2,   R_k1, GDB_REG64_OFS(GDB_FR_FPR2 ) )
	SDC1(   R_fp3,   R_k1, GDB_REG64_OFS(GDB_FR_FPR3 ) )
	SDC1(   R_fp4,   R_k1, GDB_REG64_OFS(GDB_FR_FPR4 ) )
	SDC1(   R_fp5,   R_k1, GDB_REG64_OFS(GDB_FR_FPR5 ) )
	SDC1(   R_fp6,   R_k1, GDB_REG64_OFS(GDB_FR_FPR6 ) )
	SDC1(   R_fp7,   R_k1, GDB_REG64_OFS(GDB_FR_FPR7 ) )
	SDC1(   R_fp8,   R_k1, GDB_REG64_OFS(GDB_FR_FPR8 ) )
	SDC1(   R_fp9,   R_k1, GDB_REG64_OFS(GDB_FR_FPR9 ) )
	SDC1(   R_fp10,  R_k1, GDB_REG64_OFS(GDB_FR_FPR10) )
	SDC1(   R_fp11,  R_k1, GDB_REG64_OFS(GDB_FR_FPR11) )
	SDC1(   R_fp12,  R_k1, GDB_REG64_OFS(GDB_FR_FPR12) )
	SDC1(   R_fp13,  R_k1, GDB_REG64_OFS(GDB_FR_FPR13) )
	SDC1(   R_fp14,  R_k1, GDB_REG64_OFS(GDB_FR_FPR14) )
	SDC1(   R_fp15,  R_k1, GDB_REG64_OFS(GDB_FR_FPR15) )
	SDC1(   R_fp16,  R_k1, GDB_REG64_OFS(GDB_FR_FPR16) )
	SDC1(   R_fp17,  R_k1, GDB_REG64_OFS(GDB_FR_FPR17) )
	SDC1(   R_fp18,  R_k1, GDB_REG64_OFS(GDB_FR_FPR18) )
	SDC1(   R_fp19,  R_k1, GDB_REG64_OFS(GDB_FR_FPR19) )
	SDC1(   R_fp20,  R_k1, GDB_REG64_OFS(GDB_FR_FPR20) )
	SDC1(   R_fp21,  R_k1, GDB_REG64_OFS(GDB_FR_FPR21) )
	SDC1(   R_fp22,  R_k1, GDB_REG64_OFS(GDB_FR_FPR22) )
	SDC1(   R_fp23,  R_k1, GDB_REG64_OFS(GDB_FR_FPR23) )
	SDC1(   R_fp24,  R_k1, GDB_REG64_OFS(GDB_FR_FPR24) )
	SDC1(   R_fp25,  R_k1, GDB_REG64_OFS(GDB_FR_FPR25) )
	SDC1(   R_fp26,  R_k1, GDB_REG64_OFS(GDB_FR_FPR26) )
	SDC1(   R_fp27,  R_k1, GDB_REG64_OFS(GDB_FR_FPR27) )
	SDC1(   R_fp28,  R_k1, GDB_REG64_OFS(GDB_FR_FPR28) )
	SDC1(   R_fp29,  R_k1, GDB_REG64_OFS(GDB_FR_FPR29) )
	SDC1(   R_fp30,  R_k1, GDB_REG64_OFS(GDB_FR_FPR30) )
	SDC1(   R_fp31,  R_k1, GDB_REG64_OFS(GDB_FR_FPR31) )

	b	store_control
	nop

store_fpu_gpr_32bit :	
		
	/* Store 32 bit FPU registers */
	swc1    $f0,   GDB_REG32_OFS(GDB_FR_FPR0 )(k1)
	swc1    $f1,   GDB_REG32_OFS(GDB_FR_FPR1 )(k1)
	swc1    $f2,   GDB_REG32_OFS(GDB_FR_FPR2 )(k1)	
	swc1    $f3,   GDB_REG32_OFS(GDB_FR_FPR3 )(k1)			
	swc1    $f4,   GDB_REG32_OFS(GDB_FR_FPR4 )(k1)
	swc1    $f5,   GDB_REG32_OFS(GDB_FR_FPR5 )(k1)
	swc1    $f6,   GDB_REG32_OFS(GDB_FR_FPR6 )(k1)	
	swc1    $f7,   GDB_REG32_OFS(GDB_FR_FPR7 )(k1)			
	swc1    $f8,   GDB_REG32_OFS(GDB_FR_FPR8 )(k1)
	swc1    $f9,   GDB_REG32_OFS(GDB_FR_FPR9 )(k1)
	swc1    $f10,  GDB_REG32_OFS(GDB_FR_FPR10)(k1)	
	swc1    $f11,  GDB_REG32_OFS(GDB_FR_FPR11)(k1)			
	swc1    $f12,  GDB_REG32_OFS(GDB_FR_FPR12)(k1)
	swc1    $f13,  GDB_REG32_OFS(GDB_FR_FPR13)(k1)
	swc1    $f14,  GDB_REG32_OFS(GDB_FR_FPR14)(k1)	
	swc1    $f15,  GDB_REG32_OFS(GDB_FR_FPR15)(k1)			
	swc1    $f16,  GDB_REG32_OFS(GDB_FR_FPR16)(k1)
	swc1    $f17,  GDB_REG32_OFS(GDB_FR_FPR17)(k1)
	swc1    $f18,  GDB_REG32_OFS(GDB_FR_FPR18)(k1)	
	swc1    $f19,  GDB_REG32_OFS(GDB_FR_FPR19)(k1)			
	swc1    $f20,  GDB_REG32_OFS(GDB_FR_FPR20)(k1)
	swc1    $f21,  GDB_REG32_OFS(GDB_FR_FPR21)(k1)
	swc1    $f22,  GDB_REG32_OFS(GDB_FR_FPR22)(k1)	
	swc1    $f23,  GDB_REG32_OFS(GDB_FR_FPR23)(k1)			
	swc1    $f24,  GDB_REG32_OFS(GDB_FR_FPR24)(k1)
	swc1    $f25,  GDB_REG32_OFS(GDB_FR_FPR25)(k1)
	swc1    $f26,  GDB_REG32_OFS(GDB_FR_FPR26)(k1)	
	swc1    $f27,  GDB_REG32_OFS(GDB_FR_FPR27)(k1)			
	swc1    $f28,  GDB_REG32_OFS(GDB_FR_FPR28)(k1)
	swc1    $f29,  GDB_REG32_OFS(GDB_FR_FPR29)(k1)
	swc1    $f30,  GDB_REG32_OFS(GDB_FR_FPR30)(k1)	
	swc1    $f31,  GDB_REG32_OFS(GDB_FR_FPR31)(k1)			

store_control:
	
	/* Store CP0/CP1 control registers */
	b	sys_store_control_regs
	move	a0, k1

END(store_cp1_gpr_cp0_control)

	
SLEAF( EXCEP_store_gpr_but_k0k1_ss )

        /* Just like EXCEP_store_gpr_but_k0k1ra() with the following exception :
	 * 
	 * If this is a MIPS32/MIPS64 Release 2 CPU including
	 * shadowsets, we store the GPR values of the shadowset
	 * that was in use when the exception was taken. In this case
	 * we also write k0, k1, ra.
	 */

	la	k1,  exc_context
		
	/* In case of MIPS32/MIPS64 Release 2 and
	 * BEV=0 and ERL=0, we read GPR from previous shadowset.
	 */
        la	k0, excep_cp0_regs_mask
        lw	k0, 0(k0)
        sll	k0, 31-6	/* Release 2 */
	bgez	k0, 1f
	nop
	MFC0(   k0, C0_Status )
	sll     k0, 31 - S_StatusBEV
	bltz	k0, 1f
	sll	k0, S_StatusBEV - S_StatusERL
	bgez	k0, 2f
	nop
1:
	la	k0,  sys_64bit
	lb	k0,  0(k0)
	beq	k0,  zero, 32f
	sw	$31, GDB_REG32_OFS(GDB_FR_REG31)(k1)
SET_MIPS3()
        sd	$31, GDB_REG64_OFS(GDB_FR_REG31)(k1)
SET_MIPS0()
32:
	jal	EXCEP_store_gpr_but_k0k1ra
	nop
	j	exc_handler_after_gpr
	nop	
2:
	/* Release 2 (and BEV=0 and ERL=0) */