excep_s.s

来自「MIPS YAMON, a famous monitor inc. source」· S 代码 · 共 2,069 行 · 第 1/4 页

        /* 32 bit or 64 bit */
	la	k0, sys_64bit
	lb	k0, 0(k0)
	bne	k0, zero, copy_pss_64bit
	nop

#define MOVEGPR( number )				\
	RDPGPR( R_k0, number );				\
	sw	k0,   GDB_REG32_OFS(GDB_GPR_OFS(number))(k1)

	MOVEGPR( 1  )
	MOVEGPR( 2  )
	MOVEGPR( 3  )
	MOVEGPR( 4  )
	MOVEGPR( 5  )
	MOVEGPR( 6  )
	MOVEGPR( 7  )
	MOVEGPR( 8  )
	MOVEGPR( 9  )
	MOVEGPR( 10 )
	MOVEGPR( 11 )
	MOVEGPR( 12 )
	MOVEGPR( 13 )
	MOVEGPR( 14 )
	MOVEGPR( 15 )
	MOVEGPR( 16 )
	MOVEGPR( 17 )
	MOVEGPR( 18 )
	MOVEGPR( 19 )
	MOVEGPR( 20 )
	MOVEGPR( 21 )
	MOVEGPR( 22 )
	MOVEGPR( 23 )
	MOVEGPR( 24 )
	MOVEGPR( 25 )
	MOVEGPR( 26 )
	MOVEGPR( 27 )
	MOVEGPR( 28 )
	MOVEGPR( 29 )
	MOVEGPR( 30 )
	MOVEGPR( 31 )

	j	exc_handler_after_gpr
	nop	

#undef MOVEGPR

copy_pss_64bit:

SET_MIPS3()
	
#define MOVEGPR( number )			\
	RDPGPR( R_k0, number );			\
	sd	k0,   GDB_REG64_OFS(GDB_GPR_OFS(number))(k1)

	MOVEGPR( 1  )
	MOVEGPR( 2  )
	MOVEGPR( 3  )
	MOVEGPR( 4  )
	MOVEGPR( 5  )
	MOVEGPR( 6  )
	MOVEGPR( 7  )
	MOVEGPR( 8  )
	MOVEGPR( 9  )
	MOVEGPR( 10 )
	MOVEGPR( 11 )
	MOVEGPR( 12 )
	MOVEGPR( 13 )
	MOVEGPR( 14 )
	MOVEGPR( 15 )
	MOVEGPR( 16 )
	MOVEGPR( 17 )
	MOVEGPR( 18 )
	MOVEGPR( 19 )
	MOVEGPR( 20 )
	MOVEGPR( 21 )
	MOVEGPR( 22 )
	MOVEGPR( 23 )
	MOVEGPR( 24 )
	MOVEGPR( 25 )
	MOVEGPR( 26 )
	MOVEGPR( 27 )
	MOVEGPR( 28 )
	MOVEGPR( 29 )
	MOVEGPR( 30 )
	MOVEGPR( 31 )

SET_MIPS0()

	j	exc_handler_after_gpr
	nop	

END( EXCEP_store_gpr_but_k0k1_ss )	
	
	
SLEAF( restore_control_gpr_but_k1 )

    /* Restore the CP0 registers that are available for the CPU in use.
     * 
     * k0 points to context, k1 = return address.
     *
     * We skip the following registers, since YAMON doesn't depend
     * on them and GDB doesn't request them :
     *
     * LLAddr
     * Xcontext
     * TraceControl
     * TraceControl2
     * UserTraceData
     * TraceBPC
     * PerfCnt
     * ErrCtl
     * CacheErr
     * TagLo
     * DataLo
     * TagHi
     * DataHi
     * DESAVE
     */

    /* Get availability of regs :
     *
     * Bit 0 = 32(1) or 64(0) bit CPU
     * Bit 1 = FPU
     * Bit 2 = TLB
     * Bit 3 = Watch registers
     * Bit 4 = MIPS32/MIPS64
     * ----- Following only apply to MIPS32/MIPS64
     * Bit 5 = EJTAG (MIPS32/64 only)
     * Bit 6 = MIPS32/MIPS64 Release 2
     * Bit 7 = SRSMap
     * Bit 8 = PageGrain
     */
    la		t0, excep_cp0_regs_mask
    lw		t0, 0(t0)

    /* 32 bit or 64 bit */	
    sll		t1, t0, 31-0
    bgez	t1, restore_control_64bit
    nop

    /* Registers available for all MIPS CPUs */
    lw		t1, GDB_REG32_OFS(GDB_FR_LO)(k0)
    mtlo	t1

    lw		t1, GDB_REG32_OFS(GDB_FR_HI)(k0)		
    mthi	t1

    lw		t1, GDB_REG32_OFS(GDB_FR_CAUSE)(k0)
    MTC0(	t1, C0_Cause )

    lw		t1, GDB_REG32_OFS(GDB_FR_EPC)(k0)
    MTC0(	t1, C0_EPC )

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_ERROREPC)(k0)
    MTC0(	t1, C0_ErrorEPC )

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_CONFIG)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_Config, R_C0_SelConfig )

    /* Check for TLB */
    sll		t1, t0, 31-2
    bgez	t1, 1f
    nop

    /* TLB */
    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_INDEX)(k0)
    MTC0(       t1, C0_Index )

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_ENTRYLO0)(k0)
    MTC0(	t1, C0_EntryLo0 )

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_ENTRYLO1)(k0)
    MTC0(	t1, C0_EntryLo1 )

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_CONTEXT)(k0)
    MTC0(	t1, C0_Context )

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_PAGEMASK)(k0)
    MTC0(	t1, C0_PageMask )

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_WIRED)(k0)
    MTC0(	t1, C0_Wired )

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_ENTRYHI)(k0)
    MTC0(	t1, C0_EntryHi )
1:
    /* Check for Watch registers */
    sll		t1, t0, 31-3
    bgez	t1, 1f
    nop

    /* Watch registers */
    lw	        t1, GDB_REG32_OFS(GDB_FR_CP0_WATCHLO)(k0)
    MTC0(       t1, C0_WatchLo )

    lw	        t1, GDB_REG32_OFS(GDB_FR_CP0_WATCHHI)(k0)
    MTC0(       t1, C0_WatchHi )
1:
    /* Check for MIPS32/MIPS64 */
    sll		t1, t0, 31-4
    bgez	t1, 1f
    nop

    /* MIPS32/MIPS64 */
    
    /* Config1 (required for MIPS32/MIPS64 CPUs) */
    lw	        t1, GDB_REG32_OFS(GDB_FR_CP0_CONFIG1)(k0)
    /* Config2 depends on M bit of Config1 */
    sll		t1, 31-S_ConfigMore
    bgez	t1, 2f
    nop
    lw	        t1, GDB_REG32_OFS(GDB_FR_CP0_CONFIG2)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_Config2, R_C0_SelConfig2 )
2:
    /* Check for EJTAG */
    sll		t1, t0, 31-5
    bgez	t1, 2f
    nop

    /* EJTAG regs */
#if 0 /* TBD : Consider DEBUG */
    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_DEBUG)(k0)
    MTC0(	t1, C0_Debug )
#endif

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_DEPC)(k0)
    MTC0(	t1, C0_DEPC )
2:
    /* Check for Release 2 */
    sll		t1, t0, 31-6
    bgez	t1, 2f
    nop

    /* Release 2 */
    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_HWRENA)(k0)
    MTC0(       t1, C0_HWREna )

    lw		t1, GDB_REG32_OFS(GDB_FR_CP0_INTCTL)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_IntCtl, R_C0_SelIntCtl )

    lw	        t1, GDB_REG32_OFS(GDB_FR_CP0_SRSCTL)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_SRSCtl, R_C0_SelSRSCtl )
	
    lw	        t1, GDB_REG32_OFS(GDB_FR_CP0_EBASE)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_EBase, R_C0_SelEBase )

    /* SRSMap */
    sll		t1, t0, 31-7
    bgez	t1, 2f
    nop

    lw	        t1, GDB_REG32_OFS(GDB_FR_CP0_SRSMAP)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_SRSMap, R_C0_SelSRSMap )
2:
    /* PageGrain */
    sll		t1, t0, 31-8
    bgez	t1, 1f
    nop

    lw	        t1, GDB_REG32_OFS(GDB_FR_CP0_PAGEGRAIN)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_PageGrain, R_C0_SelPageGrain )
1:
    /* Status register (always available) */
    lw		t1, GDB_REG32_OFS(GDB_FR_STATUS)(k0)
    MTC0(       t1, C0_Status)

    /* Check for FPU */
    sll		t2, t0, 31-1
    bgez	t2, EXCEP_restore_gpr_but_k1
    nop
    /* Check that FPU is enabled */
    sll		t2, t1, 31-S_StatusCU1
    bgez	t2, EXCEP_restore_gpr_but_k1
    nop

    /* Store FPU registers */
    cfc1        t2, $31 /* Empty pipeline */
    lw	        t2, GDB_REG32_OFS(GDB_FR_FSR)(k0)
    ctc1        t2, $31

    b		restore_cp1_gpr
    nop   

restore_control_64bit :	

SET_MIPS3()

    /* Registers available for all MIPS CPUs */
    ld		t1, GDB_REG64_OFS(GDB_FR_LO)(k0)
    mtlo	t1

    ld		t1, GDB_REG64_OFS(GDB_FR_HI)(k0)		
    mthi	t1

    ld		t1, GDB_REG64_OFS(GDB_FR_CAUSE)(k0)
    MTC0(	t1, C0_Cause )

    ld		t1, GDB_REG64_OFS(GDB_FR_EPC)(k0)
    DMTC0(	t1, C0_EPC )

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_ERROREPC)(k0)
    DMTC0(	t1, C0_ErrorEPC )

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_CONFIG)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_Config, R_C0_SelConfig )

    /* Check for TLB */
    sll		t1, t0, 31-2
    bgez	t1, 1f
    nop

    /* TLB */
    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_INDEX)(k0)
    MTC0(       t1, C0_Index )

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_ENTRYLO0)(k0)
    DMTC0(	t1, C0_EntryLo0 )

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_ENTRYLO1)(k0)
    DMTC0(	t1, C0_EntryLo1 )

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_CONTEXT)(k0)
    DMTC0(	t1, C0_Context )

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_PAGEMASK)(k0)
    MTC0(	t1, C0_PageMask )

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_WIRED)(k0)
    MTC0(	t1, C0_Wired )

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_ENTRYHI)(k0)
    DMTC0(	t1, C0_EntryHi )
1:
    /* Check for Watch registers */
    sll		t1, t0, 31-3
    bgez	t1, 1f
    nop

    /* Watch registers */
    ld	        t1, GDB_REG64_OFS(GDB_FR_CP0_WATCHLO)(k0)
    DMTC0(      t1, C0_WatchLo )

    ld	        t1, GDB_REG64_OFS(GDB_FR_CP0_WATCHHI)(k0)
    DMTC0(      t1, C0_WatchHi )
1:
    /* Check for MIPS32/MIPS64 */
    sll		t1, t0, 31-4
    bgez	t1, 1f
    nop

    /* MIPS32/MIPS64 */
    
    /* Config1 (required for MIPS32/MIPS64 CPUs) */
    ld	        t1, GDB_REG64_OFS(GDB_FR_CP0_CONFIG1)(k0)
    /* Config2 depends on M bit of Config1 */
    sll		t1, 31-S_ConfigMore
    bgez	t1, 2f
    nop
    ld	        t1, GDB_REG64_OFS(GDB_FR_CP0_CONFIG2)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_Config2, R_C0_SelConfig2 )
2:
    /* Check for EJTAG */
    sll		t1, t0, 31-5
    bgez	t1, 2f
    nop

    /* EJTAG regs */
#if 0 /* TBD : Consider DEBUG */
    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_DEBUG)(k0)
    MTC0(	t1, C0_Debug )
#endif

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_DEPC)(k0)
    DMTC0(	t1, C0_DEPC )
2:
    /* Check for Release 2 */
    sll		t1, t0, 31-6
    bgez	t1, 2f
    nop

    /* Release 2 */
    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_HWRENA)(k0)
    MTC0(       t1, C0_HWREna )

    ld		t1, GDB_REG64_OFS(GDB_FR_CP0_INTCTL)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_IntCtl, R_C0_SelIntCtl )

    ld	        t1, GDB_REG64_OFS(GDB_FR_CP0_SRSCTL)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_SRSCtl, R_C0_SelSRSCtl )

    ld	        t1, GDB_REG64_OFS(GDB_FR_CP0_EBASE)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_EBase, R_C0_SelEBase )

    /* SRSMap */
    sll		t1, t0, 31-7
    bgez	t1, 2f
    nop

    ld	        t1, GDB_REG64_OFS(GDB_FR_CP0_SRSMAP)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_SRSMap, R_C0_SelSRSMap )
2:
    /* PageGrain */
    sll		t1, t0, 31-8
    bgez	t1, 1f
    nop

    ld	        t1, GDB_REG64_OFS(GDB_FR_CP0_PAGEGRAIN)(k0)
    MTC0_SEL_OPCODE( R_t1, R_C0_PageGrain, R_C0_SelPageGrain )
1:
    /* Status register (always available) */
    ld		t1, GDB_REG64_OFS(GDB_FR_STATUS)(k0)
    MTC0(       t1, C0_Status)

    /* Check for FPU */
    sll		t2, t0, 31-1
    bgez	t2, EXCEP_restore_gpr_but_k1
    nop
    /* Check that FPU is enabled */
    sll		t2, t1, 31-S_StatusCU1
    bgez	t2, EXCEP_restore_gpr_but_k1
    nop

    /* Store FPU registers */
    cfc1        t2, $31 /* Empty pipeline */
    ld	        t2, GDB_REG64_OFS(GDB_FR_FSR)(k0)
    ctc1        t2, $31

SET_MIPS0()

restore_cp1_gpr:

	/* t1 contains cp0_status */
	sll	t1, 31-S_StatusFR
	bgez	t1, restore_fpu_gpr_32bit
	nop

	/* Restore 64 bit FPU registers */	
	LDC1(   R_fp0,  R_k0, GDB_REG64_OFS(GDB_FR_FPR0 ))
	LDC1(   R_fp1,  R_k0, GDB_REG64_OFS(GDB_FR_FPR1 ))
	LDC1(   R_fp2,  R_k0, GDB_REG64_OFS(GDB_FR_FPR2 ))
	LDC1(   R_fp3,  R_k0, GDB_REG64_OFS(GDB_FR_FPR3 ))
	LDC1(   R_fp4,  R_k0, GDB_REG64_OFS(GDB_FR_FPR4 ))
	LDC1(   R_fp5,  R_k0, GDB_REG64_OFS(GDB_FR_FPR5 ))
	LDC1(   R_fp6,  R_k0, GDB_REG64_OFS(GDB_FR_FPR6 ))
	LDC1(   R_fp7,  R_k0, GDB_REG64_OFS(GDB_FR_FPR7 ))
	LDC1(   R_fp8,  R_k0, GDB_REG64_OFS(GDB_FR_FPR8 ))
	LDC1(   R_fp9,  R_k0, GDB_REG64_OFS(GDB_FR_FPR9 ))
	LDC1(   R_fp10, R_k0, GDB_REG64_OFS(GDB_FR_FPR10))
	LDC1(   R_fp11, R_k0, GDB_REG64_OFS(GDB_FR_FPR11))
	LDC1(   R_fp12, R_k0, GDB_REG64_OFS(GDB_FR_FPR12))
	LDC1(   R_fp13, R_k0, GDB_REG64_OFS(GDB_FR_FPR13))
	LDC1(   R_fp14, R_k0, GDB_REG64_OFS(GDB_FR_FPR14))
	LDC1(   R_fp15, R_k0, GDB_REG64_OFS(GDB_FR_FPR15))
	LDC1(   R_fp16, R_k0, GDB_REG64_OFS(GDB_FR_FPR16))
	LDC1(   R_fp17, R_k0, GDB_REG64_OFS(GDB_FR_FPR17))
	LDC1(   R_fp18, R_k0, GDB_REG64_OFS(GDB_FR_FPR18))
	LDC1(   R_fp19, R_k0, GDB_REG64_OFS(GDB_FR_FPR19))
	LDC1(   R_fp20, R_k0, GDB_REG64_OFS(GDB_FR_FPR20))
	LDC1(   R_fp21, R_k0, GDB_REG64_OFS(GDB_FR_FPR21))
	LDC1(   R_fp22, R_k0, GDB_REG64_OFS(GDB_FR_FPR22))
	LDC1(   R_fp23, R_k0, GDB_REG64_OFS(GDB_FR_FPR23))
	LDC1(   R_fp24, R_k0, GDB_REG64_OFS(GDB_FR_FPR24))
	LDC1(   R_fp25, R_k0, GDB_REG64_OFS(GDB_FR_FPR25))
	LDC1(   R_fp26, R_k0, GDB_REG64_OFS(GDB_FR_FPR26))
	LDC1(   R_fp27, R_k0, GDB_REG64_OFS(GDB_FR_FPR27))
	LDC1(   R_fp28, R_k0, GDB_REG64_OFS(GDB_FR_FPR28))
	LDC1(   R_fp29, R_k0, GDB_REG64_OFS(GDB_FR_FPR29))
	LDC1(   R_fp30, R_k0, GDB_REG64_OFS(GDB_FR_FPR30))
	LDC1(   R_fp31, R_k0, GDB_REG64_OFS(GDB_FR_FPR31))

	b	EXCEP_restore_gpr_but_k1
	nop
	
restore_fpu_gpr_32bit :	
		
	/* Restore 32 bit FPU registers */	
	lwc1    $f0,   GDB_REG32_OFS(GDB_FR_FPR0 )(k0)
	lwc1    $f1,   GDB_REG32_OFS(GDB_FR_FPR1 )(k0)
	lwc1    $f2,   GDB_REG32_OFS(GDB_FR_FPR2 )(k0)	
	lwc1    $f3,   GDB_REG32_OFS(GDB_FR_FPR3 )(k0)			
	lwc1    $f4,   GDB_REG32_OFS(GDB_FR_FPR4 )(k0)
	lwc1    $f5,   GDB_REG32_OFS(GDB_FR_FPR5 )(k0)
	lwc1    $f6,   GDB_REG32_OFS(GDB_FR_FPR6 )(k0)	
	lwc1    $f7,   GDB_REG32_OFS(GDB_FR_FPR7 )(k0)			
	lwc1    $f8,   GDB_REG32_OFS(GDB_FR_FPR8 )(k0)
	lwc1    $f9,   GDB_REG32_OFS(GDB_FR_FPR9 )(k0)
	lwc1    $f10,  GDB_REG32_OFS(GDB_FR_FPR10)(k0)	
	lwc1    $f11,  GDB_REG32_OFS(GDB_FR_FPR11)(k0)			
	lwc1    $f12,  GDB_REG32_OFS(GDB_FR_FPR12)(k0)
	lwc1    $f13,  GDB_REG32_OFS(GDB_FR_FPR13)(k0)
	lwc1    $f14,  GDB_REG32_OFS(GDB_FR_FPR14)(k0)	
	lwc1    $f15,  GDB_REG32_OFS(GDB_FR_FPR15)(k0)			
	lwc1    $f16,  GDB_REG32_OFS(GDB_FR_FPR16)(k0)
	lwc1    $f17,  GDB_REG32_OFS(GDB_FR_FPR17)(k0)
	lwc1    $f18,  GDB_REG32_OFS(GDB_FR_FPR18)(k0)	
	lwc1    $f19,  GDB_REG32_OFS(GDB_FR_FPR19)(k0)			
	lwc1    $f20,  GDB_REG32_OFS(GDB_FR_FPR20)(k0)
	lwc1    $f21,  GDB_REG32_OFS(GDB_FR_FPR21)(k0)
	lwc1    $f22,  GDB_REG32_OFS(GDB_FR_FPR22)(k0)	
	lwc1    $f23,  GDB_REG32_OFS(GDB_FR_FPR23)(k0)			
	lwc1    $f24,  GDB_REG32_OFS(GDB_FR_FPR24)(k0)
	lwc1    $f25,  GDB_REG32_OFS(GDB_FR_FPR25)(k0)
	lwc1    $f26,  GDB_REG32_OFS(GDB_FR_FPR26)(k0)	
	lwc1    $f27,  GDB_REG32_OFS(GDB_FR_FPR27)(k0)			
	lwc1    $f28,  GDB_REG32_OFS(GDB_FR_FPR28)(k0)
	lwc1    $f29,  GDB_REG32_OFS(GDB_FR_FPR29)(k0)
	lwc1    $f30,  GDB_REG32_OFS(GDB_FR_FPR30)(k0)	
	lwc1    $f31,  GDB_REG32_OFS(GDB_FR_FPR31)(k0)

	b	EXCEP_restore_gpr_but_k1
	nop
	
END( restore_control_gpr_but_k1 )