sources.sth

该程序设计了一个产生PCM码流时序信号的模块

[Files List]
d:\Program Files\Aldec\Active-HDL 4.2\VLIB\STD\src\standard.vhd=S
d:\Program Files\Aldec\Active-HDL 4.2\VLIB\IEEE\src\stdlogic.vhd=S
D:\VHDL_EXERCISE\Active_hdl\homework\hw4\src\pcm.vhd=S
D:\VHDL_EXERCISE\Active_hdl\homework\hw4\src\test_pcm.vhd=S