pcm.vhd

该程序设计了一个产生PCM码流时序信号的模块

library ieee;
use ieee.std_logic_1164.all;

entity pcm is
port(clk:in std_logic;
	set:in std_logic;
	q1,q2,q3:out std_logic);
end pcm;

architecture arch_pcm of pcm is
signal q1_temp,q2_temp,q3_temp:std_logic:='0';
signal temp:integer:=0;
begin
process(clk,set)
variable temp:integer;
begin
	if clk'event and clk='0' and set='1' then
		q1_temp<='1';q2_temp<='0';q3_temp<='0';temp:=0;
	end if;
	if clk'event and clk='0' and q1_temp/='1' then
		temp:=temp+1;
		if q1_temp='1' and temp=3 then
			q1_temp<='0';q2_temp<='1';q3_temp<='0';temp:=0;
		elsif q2_temp='1' and temp=3 then
			q1_temp<='0';q2_temp<='0';q3_temp<='1';temp:=0;
		elsif q3_temp='1' and temp=3 then
		    q1_temp<='0';q2_temp<='0';q3_temp<='0';temp:=0;
		end if;	
	end if;
	
	if clk'event and clk='0' and q1_temp='1' then
		temp:=temp+1;
		if temp=4 then
			q1_temp<='0';q2_temp<='1';q3_temp<='0';temp:=0;
		end if;
	end if;
	
	
	
end process;
q1<=q1_temp;q2<=q2_temp;q3<=q3_temp;	
end arch_pcm;