test_pcm.vhd

来自「该程序设计了一个产生PCM码流时序信号的模块」· VHDL 代码 · 共 39 行

library ieee;
use ieee.std_logic_1164.all;

entity test_pcm is
end test_pcm;

architecture arch_test_pcm of test_pcm is
component pcm
	port(clk:in std_logic;
	set:in std_logic;
	q1,q2,q3:out std_logic);
end component;

signal clk,set,q1,q2,q3:std_logic;

begin
	u:pcm port map(clk,set,q1,q2,q3);
	
clock:process
	begin
	clk<='0';
	wait for 10 ns;
	clk<='1';
	wait for 10 ns;
end process clock;

set_lable:process
	begin
	set<='0';
	wait for 490 ns;
	set<='1';
	wait for 20 ns;	
	end process set_lable;
end arch_test_pcm;

configuration cfg_test_pcm of test_pcm is
for arch_test_pcm
end for;
end cfg_test_pcm;