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I 000031 54 242 0 cfg_test_pcm(_configuration VHDL (cfg_test_pcm 0 36 (test_pcm))
(_version v28)
(_time 1131098744595 2005.11.04 18:05:44)
(_source (\.\\src\\test_pcm.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_architecture arch_test_pcm
)
)
I 000049 55 1988 1131098744584 arch_pcm(_unit VHDL (pcm 0 4 (arch_pcm 0 10 ))
(_version v28)
(_time 1131098744584 2005.11.04 18:05:44)
(_source (\.\\src\\pcm.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1130938396124)
(_use )
)
(_object
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 5 (_entity (_in ))))
(_port (_internal set ~extieee.std_logic_1164.std_logic 0 6 (_entity (_in ))))
(_port (_internal q1 ~extieee.std_logic_1164.std_logic 0 7 (_entity (_out ))))
(_port (_internal q2 ~extieee.std_logic_1164.std_logic 0 7 (_entity (_out ))))
(_port (_internal q3 ~extieee.std_logic_1164.std_logic 0 7 (_entity (_out ))))
(_signal (_internal q1_temp ~extieee.std_logic_1164.std_logic 0 11 (_architecture (_uni ((i 2))))))
(_signal (_internal q2_temp ~extieee.std_logic_1164.std_logic 0 11 (_architecture (_uni ((i 2))))))
(_signal (_internal q3_temp ~extieee.std_logic_1164.std_logic 0 11 (_architecture (_uni ((i 2))))))
(_signal (_internal temp ~extSTD.STANDARD.INTEGER 0 12 (_architecture (_uni ((i 0))))))
(_variable (_internal temp ~extSTD.STANDARD.INTEGER 0 15 (_process 0 )))
(_process
(line__14(_architecture 0 0 14 (_process (_target(5)(6)(7))(_sensitivity(1)(0))(_read(5)(6)(7)))))
(line__41(_architecture 1 0 41 (_assignment (_alias((q1)(q1_temp)))(_target(2))(_sensitivity(5)))))
(line__41__1(_architecture 2 0 41 (_assignment (_alias((q2)(q2_temp)))(_target(3))(_sensitivity(6)))))
(line__41__2(_architecture 3 0 41 (_assignment (_alias((q3)(q3_temp)))(_target(4))(_sensitivity(7)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))
)
(_model . arch_pcm 4 -1
)
)
I 000054 55 1912 1131098744594 arch_test_pcm(_unit VHDL (test_pcm 0 4 (arch_test_pcm 0 7 ))
(_version v28)
(_time 1131098744594 2005.11.04 18:05:44)
(_source (\.\\src\\test_pcm.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1130939747327)
(_use )
)
(_component
(pcm
(_object
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 9 (_entity (_in ))))
(_port (_internal set ~extieee.std_logic_1164.std_logic 0 10 (_entity (_in ))))
(_port (_internal q1 ~extieee.std_logic_1164.std_logic 0 11 (_entity (_out ))))
(_port (_internal q2 ~extieee.std_logic_1164.std_logic 0 11 (_entity (_out ))))
(_port (_internal q3 ~extieee.std_logic_1164.std_logic 0 11 (_entity (_out ))))
)
)
)
(_instantiation u 0 17 (_component pcm )
(_port
((clk)(clk))
((set)(set))
((q1)(q1))
((q2)(q2))
((q3)(q3))
)
(_use (_entity . pcm)
)
)
(_object
(_signal (_internal clk ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_signal (_internal set ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_signal (_internal q1 ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_signal (_internal q2 ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_signal (_internal q3 ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_process
(clock(_architecture 0 0 19 (_process (_wait_for)(_target(0)))))
(set_lable(_architecture 1 0 27 (_process (_wait_for)(_target(1)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
)
(_model . arch_test_pcm 2 -1
)
)
V 000049 55 1988 1131098746949 arch_pcm(_unit VHDL (pcm 0 4 (arch_pcm 0 10 ))
(_version v28)
(_time 1131098746948 2005.11.04 18:05:46)
(_source (\.\\src\\pcm.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1130938396124)
(_use )
)
(_object
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 5 (_entity (_in ))))
(_port (_internal set ~extieee.std_logic_1164.std_logic 0 6 (_entity (_in ))))
(_port (_internal q1 ~extieee.std_logic_1164.std_logic 0 7 (_entity (_out ))))
(_port (_internal q2 ~extieee.std_logic_1164.std_logic 0 7 (_entity (_out ))))
(_port (_internal q3 ~extieee.std_logic_1164.std_logic 0 7 (_entity (_out ))))
(_signal (_internal q1_temp ~extieee.std_logic_1164.std_logic 0 11 (_architecture (_uni ((i 2))))))
(_signal (_internal q2_temp ~extieee.std_logic_1164.std_logic 0 11 (_architecture (_uni ((i 2))))))
(_signal (_internal q3_temp ~extieee.std_logic_1164.std_logic 0 11 (_architecture (_uni ((i 2))))))
(_signal (_internal temp ~extSTD.STANDARD.INTEGER 0 12 (_architecture (_uni ((i 0))))))
(_variable (_internal temp ~extSTD.STANDARD.INTEGER 0 15 (_process 0 )))
(_process
(line__14(_architecture 0 0 14 (_process (_target(5)(6)(7))(_sensitivity(1)(0))(_read(5)(6)(7)))))
(line__41(_architecture 1 0 41 (_assignment (_alias((q1)(q1_temp)))(_target(2))(_sensitivity(5)))))
(line__41__1(_architecture 2 0 41 (_assignment (_alias((q2)(q2_temp)))(_target(3))(_sensitivity(6)))))
(line__41__2(_architecture 3 0 41 (_assignment (_alias((q3)(q3_temp)))(_target(4))(_sensitivity(7)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))
)
(_model . arch_pcm 4 -1
)
)
V 000054 55 1912 1131098746959 arch_test_pcm(_unit VHDL (test_pcm 0 4 (arch_test_pcm 0 7 ))
(_version v28)
(_time 1131098746958 2005.11.04 18:05:46)
(_source (\.\\src\\test_pcm.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1130939747327)
(_use )
)
(_component
(pcm
(_object
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 9 (_entity (_in ))))
(_port (_internal set ~extieee.std_logic_1164.std_logic 0 10 (_entity (_in ))))
(_port (_internal q1 ~extieee.std_logic_1164.std_logic 0 11 (_entity (_out ))))
(_port (_internal q2 ~extieee.std_logic_1164.std_logic 0 11 (_entity (_out ))))
(_port (_internal q3 ~extieee.std_logic_1164.std_logic 0 11 (_entity (_out ))))
)
)
)
(_instantiation u 0 17 (_component pcm )
(_port
((clk)(clk))
((set)(set))
((q1)(q1))
((q2)(q2))
((q3)(q3))
)
(_use (_entity . pcm)
)
)
(_object
(_signal (_internal clk ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_signal (_internal set ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_signal (_internal q1 ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_signal (_internal q2 ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_signal (_internal q3 ~extieee.std_logic_1164.std_logic 0 14 (_architecture (_uni ))))
(_process
(clock(_architecture 0 0 19 (_process (_wait_for)(_target(0)))))
(set_lable(_architecture 1 0 27 (_process (_wait_for)(_target(1)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
)
(_model . arch_test_pcm 2 -1
)
)
V 000031 54 242 0 cfg_test_pcm(_configuration VHDL (cfg_test_pcm 0 36 (test_pcm))
(_version v28)
(_time 1131098746959 2005.11.04 18:05:46)
(_source (\.\\src\\test_pcm.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_architecture arch_test_pcm
)
)
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