counter10.vhd

来自「该程序实现的是10进制的计数器」· VHDL 代码 · 共 41 行

Library IEEE;
use IEEE.std_logic_1164.all;
Entity counter_10 Is
port(	reset : in std_logic; 
    up_enable : in std_logic;
          clk : in std_logic;
	count : out  std_logic;
          bcd : out integer range 0 to 9
      );
end counter_10;

Architecture counter10_arch of counter_10 is
begin
signal bcd_temp : integer range 0 to 9;

process(clk,reset)
begin

       if reset='1' then
	      count <=0;
		  bcd<=0;
	      bcd_temp:=0;
	  elsif clk='1' and clk'event then
		if up_enable='1' then
		    if bcd_temp=8 then
 	  	       count <='1';
		       bcd_temp<=bcd_temp+1;
		    elsif bcd_temp=9 then
		       count <='0';
		       bcd_temp<='0';
			else
			   count <='0';
			   bcd_temp<=bcd_temp+1;

		    end if;
		end if;
       end if;
	bcd <= bcd_temp;
end process;

end counter10_arch;