tb_counter10.vhd

来自「该程序实现的是10进制的计数器」· VHDL 代码 · 共 35 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

Entity E is
End E;

Architecture A of E is
begin
signal reset:std_logic; 
signal up_enable:std_logic;
signal clk:std_logic;
signal count:integer range 0 to 1;
signal bcd:integer range 0 to 9;

component counter_10
port(	reset : in std_logic; 
    up_enable : in std_logic;
          clk : in std_logic;
	    count : out integer range 0 to 1;
          bcd : out integer range 0 to 9
      );
end component;
TB : block
begin
process begin
reset <= '0';
up_enable <= '1';
clk <= '0';
wait for 10 ns;
clk <= '1';
end process;
end block;
end A;