counter10.srs

该程序实现的是10进制的计数器

#
#
#
# Created by Synplify VHDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Tue Nov 01 20:53:41 2005
#
#
#OPTIONS:"|-autosm|-fid2|-sharing|on|-encrypt|-ui|-lite|-pro|-ram|-ignore_undefined_lib|-ll|2000|-lib|work"
#CUR:"D:\\Program Files\\Synplicity\\fpga_81\\bin\\c_vhdl.exe":1115125640
#CUR:"D:\\Program Files\\Synplicity\\fpga_81\\lib\\vhd\\location.map":1114701536
#CUR:"D:\\Program Files\\Synplicity\\fpga_81\\lib\\vhd\\std.vhd":1111509844
#CUR:"D:\\Program Files\\Synplicity\\fpga_81\\lib\\vhd\\std.vhd":1111509844
#CUR:"D:\\VHDL_EXERCISE\\counter10\\counter10.vhd":1130835310
#CUR:"D:\\VHDL_EXERCISE\\counter10\\counter10.vhd":1130835310
#CUR:"D:\\VHDL_EXERCISE\\counter10\\counter10.vhd":1130835310
#CUR:"D:\\VHDL_EXERCISE\\counter10\\counter10.vhd":1130835310
#CUR:"D:\\Program Files\\Synplicity\\fpga_81\\lib\\vhd\\std1164.vhd":927285456
#CUR:"D:\\Program Files\\Synplicity\\fpga_81\\lib\\vhd\\std1164.vhd":927285456
f "D:\Program Files\Synplicity\fpga_81\lib\vhd\std.vhd"; # file 0
af .is_vhdl 1;
f "D:\VHDL_EXERCISE\counter10\counter10.vhd"; # file 1
af .is_vhdl 1;
f "D:\Program Files\Synplicity\fpga_81\lib\vhd\std1164.vhd"; # file 2
af .is_vhdl 1;
@E
@ 
ftell;
@E@MR@64::6(::R4nI	FsRkOFMs0C_R4jOMFk04Csjs_NO
E;N3PRHE#P84DR;P
NR#3H_8PED;R4
RNP3M#$_NVlbIR"FRs	\:"7\]\e7 p_XB )Q\1 \kOFMs0C4\j\OMFk04CsjE3P8
\""
;

@HR@n4::nn::R4jsCC#0CRs#;C0
@HR@(4::(c::R4.kCb_MDNLCbRk_NCML;DC
@HR@U4:::4jU.:4R	ODR	OD;



@FR@g4::g4::O6RF0kMrRj9V#NDCN;
H#R3$NM_s$sNb0FsR
4;
@FR@44:jj:4::4j4L.ROd8r:Rj9V#NDCN,VD,#CV#NDCN,VD;#C
@bR@4j::44::0.RsRkC0CskRk0sCb;
Rj@@:44::.4:RDVN#VCRNCD#RDVN#
C;C
;