counter10.tlg

该程序实现的是10进制的计数器

@N:"D:\VHDL_EXERCISE\counter10\counter10.vhd":5:7:5:16|Synthesizing work.counter_10.counter10_arch 
Post processing for work.counter_10.counter10_arch
@W: CL190 :"D:\VHDL_EXERCISE\counter10\counter10.vhd":20:7:20:8|Optimizing register bit bcd_temp(3) to a constant 0
@W: CL190 :"D:\VHDL_EXERCISE\counter10\counter10.vhd":20:7:20:8|Optimizing register bit bcd_temp(0) to a constant 0
@W: CL190 :"D:\VHDL_EXERCISE\counter10\counter10.vhd":20:7:20:8|Optimizing register bit bcd_temp(1) to a constant 0
@W: CL190 :"D:\VHDL_EXERCISE\counter10\counter10.vhd":20:7:20:8|Optimizing register bit bcd_temp(2) to a constant 0
@W: CL159 :"D:\VHDL_EXERCISE\counter10\counter10.vhd":6:6:6:10|Input reset is unused
@W: CL159 :"D:\VHDL_EXERCISE\counter10\counter10.vhd":7:4:7:12|Input up_enable is unused
@W: CL159 :"D:\VHDL_EXERCISE\counter10\counter10.vhd":8:10:8:12|Input clk is unused