counter10.srr

来自「该程序实现的是10进制的计数器」· SRR 代码 · 共 18 行

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Tue Nov 01 21:02:40 2005

Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@N:"D:\VHDL_EXERCISE\counter10\counter10.vhd":3:7:3:16|Top entity is set to counter_10.
@E: CD214 :"D:\VHDL_EXERCISE\counter10\counter10.vhd":14:0:14:5|Not a concurrent statement
1 error parsing file D:\VHDL_EXERCISE\counter10\counter10.vhd
@END
@E|Parse errors encountered - exiting
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 01 21:02:42 2005