sub_full_n.srr

该程序实现的N位全减器

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Mon Oct 31 13:04:10 2005

Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@N:"D:\VHDL_EXERCISE\sub_full_n\sub_full_n.vhd":1:7:1:16|Top entity is set to sub_full_n.
VHDL syntax check successful!
File D:\VHDL_EXERCISE\project1\sub_full.vhd changed - recompiling
@N:"D:\VHDL_EXERCISE\sub_full_n\sub_full_n.vhd":1:7:1:16|Synthesizing work.sub_full_n.sub_full_n 
@W: CD453 :"D:\VHDL_EXERCISE\sub_full_n\sub_full_n.vhd":21:37:21:44|Index 0 may be out of range
@W: CD453 :"D:\VHDL_EXERCISE\sub_full_n\sub_full_n.vhd":29:33:29:37|Index 0 may be out of range
@N:"D:\VHDL_EXERCISE\sub_full_n\sub_full.vhd":1:7:1:14|Synthesizing work.sub_full.sub_full 
Post processing for work.sub_full.sub_full
Post processing for work.sub_full_n.sub_full_n
@W: CL167 :"D:\VHDL_EXERCISE\sub_full_n\sub_full_n.vhd":29:0:29:1|Input b_in of instance u3 is floating
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Oct 31 13:04:10 2005

###########################################################[
Version 8.1
Synplicity Proasic Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
@W: BN215 |Library scaling: cannot find default operating conditions - failed to scale design


RTL optimization done.

Added 0 Buffers
Added 0 Cells via replication
Writing Analyst data base D:\VHDL_EXERCISE\sub_full_n\rev_3\sub_full_n.srm
Writing EDIF Netlist and constraint files


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Oct 31 13:04:11 2005
#


Top view:               sub_full_n
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell sub_full_n.sub_full_n
  Cell usage:
              cell count     area count*area
              IB33    17      0.0        0.0
              XOR2    14      1.0       14.0
            OB33PH     9      0.0        0.0
               PWR     9      0.0        0.0
               GND     9      0.0        0.0
          AOI21TTF     5      1.0        5.0
           OA21TTF     4      1.0        4.0
          OAI21TTF     1      1.0        1.0
            NOR2FT     1      1.0        1.0
            XOR2FT     1      1.0        1.0
           OA21FTT     1      1.0        1.0
          OAI21FTT     1      1.0        1.0
                   -----          ----------
             TOTAL    72                28.0
Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]