sub_full_n.tlg

该程序实现的N位全减器

@N:"D:\VHDL_EXERCISE\sub_full_n\sub_full_n.vhd":1:7:1:16|Synthesizing work.sub_full_n.sub_full_n 
@W: CD453 :"D:\VHDL_EXERCISE\sub_full_n\sub_full_n.vhd":21:37:21:44|Index 0 may be out of range
@W: CD453 :"D:\VHDL_EXERCISE\sub_full_n\sub_full_n.vhd":29:33:29:37|Index 0 may be out of range
@N:"D:\VHDL_EXERCISE\sub_full_n\sub_full.vhd":1:7:1:14|Synthesizing work.sub_full.sub_full 
Post processing for work.sub_full.sub_full
Post processing for work.sub_full_n.sub_full_n
@W: CL167 :"D:\VHDL_EXERCISE\sub_full_n\sub_full_n.vhd":29:0:29:1|Input b_in of instance u3 is floating