reg_comp.map.qmsg

4X4 KEYPAD 的密码比较模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 31 05:27:31 2004 " "Info: Processing started: Sun Oct 31 05:27:31 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off reg_comp -c reg_comp " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off reg_comp -c reg_comp" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg_comp.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg_comp.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg_comp-reg_comp_architecture " "Info: Found design unit 1: reg_comp-reg_comp_architecture" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "reg_comp-reg_comp_architecture" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 52 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg_comp " "Info: Found entity 1: reg_comp" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "reg_comp" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 35 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "temp_din10\[3\] dout10\[3\]~reg0 " "Info: Duplicate register temp_din10\[3\] merged to single register dout10\[3\]~reg0" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp_din10\[2\] dout10\[2\]~reg0 " "Info: Duplicate register temp_din10\[2\] merged to single register dout10\[2\]~reg0" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp_din10\[1\] dout10\[1\]~reg0 " "Info: Duplicate register temp_din10\[1\] merged to single register dout10\[1\]~reg0" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp_din10\[0\] dout10\[0\]~reg0 " "Info: Duplicate register temp_din10\[0\] merged to single register dout10\[0\]~reg0" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp_din1\[3\] dout1\[3\]~reg0 " "Info: Duplicate register temp_din1\[3\] merged to single register dout1\[3\]~reg0" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp_din1\[2\] dout1\[2\]~reg0 " "Info: Duplicate register temp_din1\[2\] merged to single register dout1\[2\]~reg0" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp_din1\[1\] dout1\[1\]~reg0 " "Info: Duplicate register temp_din1\[1\] merged to single register dout1\[1\]~reg0" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp_din1\[0\] dout1\[0\]~reg0 " "Info: Duplicate register temp_din1\[0\] merged to single register dout1\[0\]~reg0" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "Netlist Optimizations " "Warning: Feature Netlist Optimizations is not available with your current license" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "35 " "Info: Implemented 35 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 31 05:27:33 2004 " "Info: Processing ended: Sun Oct 31 05:27:33 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}