reg_comp.fit.qmsg

4X4 KEYPAD 的密码比较模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 31 05:27:33 2004 " "Info: Processing started: Sun Oct 31 05:27:33 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off reg_comp -c reg_comp " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off reg_comp -c reg_comp" {  } {  } 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "reg_comp EP20K30ETC144-1 " "Info: Automatically selected device EP20K30ETC144-1 for design reg_comp" {  } {  } 0}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "SignalProbe " "Warning: Feature SignalProbe is not available with your current license" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "clk automatically " "Info: Promoted cell clk to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "reset automatically " "Info: Promoted cell reset to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Sun Oct 31 2004 05:27:35 " "Info: Started fitting attempt 1 on Sun Oct 31 2004 at 05:27:35" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "1 " "Info: Overall column FastTrack interconnect = 1%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "1 " "Info: Overall row FastTrack interconnect = 1%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "1 " "Info: Maximum column FastTrack interconnect = 1%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "4 " "Info: Maximum row FastTrack interconnect = 4%" {  } {  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.166 ns register register " "Info: Estimated most critical path is register to register delay of 2.166 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns dout1\[2\]~reg0 1 REG LAB_7_E1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LAB_7_E1; Fanout = 2; REG Node = 'dout1\[2\]~reg0'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { dout1[2]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.890 ns) 1.297 ns process0~105 2 COMB LAB_7_E1 1 " "Info: 2: + IC(0.246 ns) + CELL(0.890 ns) = 1.297 ns; Loc. = LAB_7_E1; Fanout = 1; COMB Node = 'process0~105'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.136 ns" { dout1[2]~reg0 process0~105 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.623 ns) 2.166 ns result~reg0 3 REG LAB_6_E1 1 " "Info: 3: + IC(0.246 ns) + CELL(0.623 ns) = 2.166 ns; Loc. = LAB_6_E1; Fanout = 1; REG Node = 'result~reg0'" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "0.869 ns" { process0~105 result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.674 ns 77.29 % " "Info: Total cell delay = 1.674 ns ( 77.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.492 ns 22.71 % " "Info: Total interconnect delay = 0.492 ns ( 22.71 % )" {  } {  } 0}  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "2.166 ns" { dout1[2]~reg0 process0~105 result~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 31 05:27:37 2004 " "Info: Processing ended: Sun Oct 31 05:27:37 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}