📄 reg_comp.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 40 -1 0 } } { "c:/altera/quartus41sp2/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41sp2/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register dout1\[0\]~reg0 result~reg0 290.02 MHz Internal " "Info: Clock clk Internal fmax is restricted to 290.02 MHz between source register dout1\[0\]~reg0 and destination register result~reg0" { { "Info" "ITDB_CLOCK_RATE" "clock 3.448 ns " "Info: fmax restricted to clock pin edge rate 3.448 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.095 ns + Longest register register " "Info: + Longest register to register delay is 2.095 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns dout1\[0\]~reg0 1 REG LC10_6_E1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC10_6_E1; Fanout = 2; REG Node = 'dout1\[0\]~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { dout1[0]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.798 ns) 1.219 ns process0~104 2 COMB LC4_6_E1 1 " "Info: 2: + IC(0.260 ns) + CELL(0.798 ns) = 1.219 ns; Loc. = LC4_6_E1; Fanout = 1; COMB Node = 'process0~104'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.058 ns" { dout1[0]~reg0 process0~104 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.623 ns) 2.095 ns result~reg0 3 REG LC2_6_E1 1 " "Info: 3: + IC(0.253 ns) + CELL(0.623 ns) = 2.095 ns; Loc. = LC2_6_E1; Fanout = 1; REG Node = 'result~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "0.876 ns" { process0~104 result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.582 ns 75.51 % " "Info: Total cell delay = 1.582 ns ( 75.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.513 ns 24.49 % " "Info: Total interconnect delay = 0.513 ns ( 24.49 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "2.095 ns" { dout1[0]~reg0 process0~104 result~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.663 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 9 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns result~reg0 2 REG LC2_6_E1 1 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC2_6_E1; Fanout = 1; REG Node = 'result~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "0.773 ns" { clk result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.52 % " "Info: Total cell delay = 0.890 ns ( 53.52 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns 46.48 % " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk result~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.663 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 9 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns dout1\[0\]~reg0 2 REG LC10_6_E1 2 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC10_6_E1; Fanout = 2; REG Node = 'dout1\[0\]~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "0.773 ns" { clk dout1[0]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.52 % " "Info: Total cell delay = 0.890 ns ( 53.52 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns 46.48 % " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk dout1[0]~reg0 } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk dout1[0]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "2.095 ns" { dout1[0]~reg0 process0~104 result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk dout1[0]~reg0 } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { result~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "dout10\[3\]~reg0 RE clk 5.969 ns register " "Info: tsu for register dout10\[3\]~reg0 (data pin = RE, clock pin = clk) is 5.969 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.434 ns + Longest pin register " "Info: + Longest pin to register delay is 7.434 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns RE 1 PIN PIN_30 1 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_30; Fanout = 1; PIN Node = 'RE'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { RE } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.296 ns) + CELL(0.358 ns) 5.894 ns dout10\[3\]~8 2 COMB LC3_7_E1 8 " "Info: 2: + IC(4.296 ns) + CELL(0.358 ns) = 5.894 ns; Loc. = LC3_7_E1; Fanout = 8; COMB Node = 'dout10\[3\]~8'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "4.654 ns" { RE dout10[3]~8 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.509 ns) 7.434 ns dout10\[3\]~reg0 3 REG LC6_6_E1 2 " "Info: 3: + IC(1.031 ns) + CELL(0.509 ns) = 7.434 ns; Loc. = LC6_6_E1; Fanout = 2; REG Node = 'dout10\[3\]~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.540 ns" { dout10[3]~8 dout10[3]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.107 ns 28.34 % " "Info: Total cell delay = 2.107 ns ( 28.34 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.327 ns 71.66 % " "Info: Total interconnect delay = 5.327 ns ( 71.66 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "7.434 ns" { RE dout10[3]~8 dout10[3]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.663 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 9 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns dout10\[3\]~reg0 2 REG LC6_6_E1 2 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC6_6_E1; Fanout = 2; REG Node = 'dout10\[3\]~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "0.773 ns" { clk dout10[3]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.52 % " "Info: Total cell delay = 0.890 ns ( 53.52 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns 46.48 % " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk dout10[3]~reg0 } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "7.434 ns" { RE dout10[3]~8 dout10[3]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk dout10[3]~reg0 } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout10\[0\] dout10\[0\]~reg0 6.859 ns register " "Info: tco from clock clk to destination pin dout10\[0\] through register dout10\[0\]~reg0 is 6.859 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.663 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 9 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns dout10\[0\]~reg0 2 REG LC5_6_E1 2 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC5_6_E1; Fanout = 2; REG Node = 'dout10\[0\]~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "0.773 ns" { clk dout10[0]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.52 % " "Info: Total cell delay = 0.890 ns ( 53.52 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns 46.48 % " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk dout10[0]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.861 ns + Longest register pin " "Info: + Longest register to pin delay is 4.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns dout10\[0\]~reg0 1 REG LC5_6_E1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC5_6_E1; Fanout = 2; REG Node = 'dout10\[0\]~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { dout10[0]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.290 ns) + CELL(2.410 ns) 4.861 ns dout10\[0\] 2 PIN PIN_26 0 " "Info: 2: + IC(2.290 ns) + CELL(2.410 ns) = 4.861 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'dout10\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "4.700 ns" { dout10[0]~reg0 dout10[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.571 ns 52.89 % " "Info: Total cell delay = 2.571 ns ( 52.89 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.290 ns 47.11 % " "Info: Total interconnect delay = 2.290 ns ( 47.11 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "4.861 ns" { dout10[0]~reg0 dout10[0] } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk dout10[0]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "4.861 ns" { dout10[0]~reg0 dout10[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "dout10\[0\]~reg0 din10\[0\] clk -3.012 ns register " "Info: th for register dout10\[0\]~reg0 (data pin = din10\[0\], clock pin = clk) is -3.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.663 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 9 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns dout10\[0\]~reg0 2 REG LC5_6_E1 2 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC5_6_E1; Fanout = 2; REG Node = 'dout10\[0\]~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "0.773 ns" { clk dout10[0]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.52 % " "Info: Total cell delay = 0.890 ns ( 53.52 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns 46.48 % " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk dout10[0]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.364 ns + " "Info: + Micro hold delay of destination is 0.364 ns" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.039 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.039 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.310 ns) 1.310 ns din10\[0\] 1 PIN PIN_64 2 " "Info: 1: + IC(0.000 ns) + CELL(1.310 ns) = 1.310 ns; Loc. = PIN_64; Fanout = 2; PIN Node = 'din10\[0\]'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "" { din10[0] } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 39 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.650 ns) + CELL(0.079 ns) 5.039 ns dout10\[0\]~reg0 2 REG LC5_6_E1 2 " "Info: 2: + IC(3.650 ns) + CELL(0.079 ns) = 5.039 ns; Loc. = LC5_6_E1; Fanout = 2; REG Node = 'dout10\[0\]~reg0'" { } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "3.729 ns" { din10[0] dout10[0]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/reg_comp.vhd" 59 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns 27.56 % " "Info: Total cell delay = 1.389 ns ( 27.56 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.650 ns 72.44 % " "Info: Total interconnect delay = 3.650 ns ( 72.44 % )" { } { } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "5.039 ns" { din10[0] dout10[0]~reg0 } "NODE_NAME" } } } } 0} } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "1.663 ns" { clk dout10[0]~reg0 } "NODE_NAME" } } } { "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" "" "" { Report "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp_cmp.qrpt" Compiler "reg_comp" "UNKNOWN" "V1" "D:/document/personal/inLiverpool/VHDL/project/assignment1/project/module/reg_comp/db/reg_comp.quartus_db" { Floorplan "" "" "5.039 ns" { din10[0] dout10[0]~reg0 } "NODE_NAME" } } } } 0}
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