reg_comp.tan.rpt

4X4 KEYPAD 的密码比较模块

; N/A   ; None         ; 6.835 ns   ; dout10[1]~reg0 ; dout10[1] ; clk        ;
; N/A   ; None         ; 6.223 ns   ; dout1[3]~reg0  ; dout1[3]  ; clk        ;
; N/A   ; None         ; 5.664 ns   ; dout10[2]~reg0 ; dout10[2] ; clk        ;
; N/A   ; None         ; 5.664 ns   ; dout10[3]~reg0 ; dout10[3] ; clk        ;
; N/A   ; None         ; 5.660 ns   ; dout1[2]~reg0  ; dout1[2]  ; clk        ;
; N/A   ; None         ; 5.628 ns   ; dout1[1]~reg0  ; dout1[1]  ; clk        ;
; N/A   ; None         ; 5.627 ns   ; result~reg0    ; result    ; clk        ;
+-------+--------------+------------+----------------+-----------+------------+


+---------------------------------------------------------------------------------+
; th                                                                              ;
+---------------+-------------+-----------+-----------+----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To             ; To Clock ;
+---------------+-------------+-----------+-----------+----------------+----------+
; N/A           ; None        ; -3.012 ns ; din10[0]  ; dout10[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.036 ns ; din10[3]  ; dout10[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.048 ns ; din10[1]  ; dout10[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.136 ns ; din10[2]  ; dout10[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.418 ns ; din1[3]   ; dout1[3]~reg0  ; clk      ;
; N/A           ; None        ; -3.466 ns ; read_comp ; result~reg0    ; clk      ;
; N/A           ; None        ; -3.498 ns ; din1[0]   ; dout1[0]~reg0  ; clk      ;
; N/A           ; None        ; -3.526 ns ; din1[1]   ; dout1[1]~reg0  ; clk      ;
; N/A           ; None        ; -3.593 ns ; din1[2]   ; dout1[2]~reg0  ; clk      ;
; N/A           ; None        ; -4.080 ns ; din1[3]   ; result~reg0    ; clk      ;
; N/A           ; None        ; -4.137 ns ; din10[1]  ; result~reg0    ; clk      ;
; N/A           ; None        ; -4.514 ns ; read_comp ; dout10[2]~reg0 ; clk      ;
; N/A           ; None        ; -4.514 ns ; read_comp ; dout1[2]~reg0  ; clk      ;
; N/A           ; None        ; -4.562 ns ; din10[0]  ; result~reg0    ; clk      ;
; N/A           ; None        ; -4.622 ns ; RE        ; dout10[2]~reg0 ; clk      ;
; N/A           ; None        ; -4.622 ns ; RE        ; dout1[2]~reg0  ; clk      ;
; N/A           ; None        ; -4.633 ns ; din1[1]   ; result~reg0    ; clk      ;
; N/A           ; None        ; -4.672 ns ; din10[3]  ; result~reg0    ; clk      ;
; N/A           ; None        ; -4.695 ns ; din1[0]   ; result~reg0    ; clk      ;
; N/A           ; None        ; -4.745 ns ; din10[2]  ; result~reg0    ; clk      ;
; N/A           ; None        ; -4.759 ns ; din1[2]   ; result~reg0    ; clk      ;
; N/A           ; None        ; -5.291 ns ; read_comp ; dout1[3]~reg0  ; clk      ;
; N/A           ; None        ; -5.297 ns ; read_comp ; dout1[0]~reg0  ; clk      ;
; N/A           ; None        ; -5.298 ns ; read_comp ; dout10[1]~reg0 ; clk      ;
; N/A           ; None        ; -5.298 ns ; read_comp ; dout10[0]~reg0 ; clk      ;
; N/A           ; None        ; -5.299 ns ; read_comp ; dout10[3]~reg0 ; clk      ;
; N/A           ; None        ; -5.299 ns ; read_comp ; dout1[1]~reg0  ; clk      ;
; N/A           ; None        ; -5.399 ns ; RE        ; dout1[3]~reg0  ; clk      ;
; N/A           ; None        ; -5.405 ns ; RE        ; dout1[0]~reg0  ; clk      ;
; N/A           ; None        ; -5.406 ns ; RE        ; dout10[1]~reg0 ; clk      ;
; N/A           ; None        ; -5.406 ns ; RE        ; dout10[0]~reg0 ; clk      ;
; N/A           ; None        ; -5.407 ns ; RE        ; dout10[3]~reg0 ; clk      ;
; N/A           ; None        ; -5.407 ns ; RE        ; dout1[1]~reg0  ; clk      ;
+---------------+-------------+-----------+-----------+----------------+----------+


+---------------------------------------------------------------------------------------------+
; Minimum tco                                                                                 ;
+---------------+------------------+----------------+----------------+-----------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From           ; To        ; From Clock ;
+---------------+------------------+----------------+----------------+-----------+------------+
; N/A           ; None             ; 5.627 ns       ; result~reg0    ; result    ; clk        ;
; N/A           ; None             ; 5.628 ns       ; dout1[1]~reg0  ; dout1[1]  ; clk        ;
; N/A           ; None             ; 5.660 ns       ; dout1[2]~reg0  ; dout1[2]  ; clk        ;
; N/A           ; None             ; 5.664 ns       ; dout10[3]~reg0 ; dout10[3] ; clk        ;
; N/A           ; None             ; 5.664 ns       ; dout10[2]~reg0 ; dout10[2] ; clk        ;
; N/A           ; None             ; 6.223 ns       ; dout1[3]~reg0  ; dout1[3]  ; clk        ;
; N/A           ; None             ; 6.835 ns       ; dout10[1]~reg0 ; dout10[1] ; clk        ;
; N/A           ; None             ; 6.841 ns       ; dout1[0]~reg0  ; dout1[0]  ; clk        ;
; N/A           ; None             ; 6.859 ns       ; dout10[0]~reg0 ; dout10[0] ; clk        ;
+---------------+------------------+----------------+----------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Sun Oct 31 05:27:40 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off reg_comp -c reg_comp
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 290.02 MHz between source register dout1[0]~reg0 and destination register result~reg0
    Info: fmax restricted to clock pin edge rate 3.448 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.095 ns
            Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC10_6_E1; Fanout = 2; REG Node = 'dout1[0]~reg0'
            Info: 2: + IC(0.260 ns) + CELL(0.798 ns) = 1.219 ns; Loc. = LC4_6_E1; Fanout = 1; COMB Node = 'process0~104'
            Info: 3: + IC(0.253 ns) + CELL(0.623 ns) = 2.095 ns; Loc. = LC2_6_E1; Fanout = 1; REG Node = 'result~reg0'
            Info: Total cell delay = 1.582 ns ( 75.51 % )
            Info: Total interconnect delay = 0.513 ns ( 24.49 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 1.663 ns
                Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'
                Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC2_6_E1; Fanout = 1; REG Node = 'result~reg0'
                Info: Total cell delay = 0.890 ns ( 53.52 % )
                Info: Total interconnect delay = 0.773 ns ( 46.48 % )
            Info: - Longest clock path from clock clk to source register is 1.663 ns
                Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'
                Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC10_6_E1; Fanout = 2; REG Node = 'dout1[0]~reg0'
                Info: Total cell delay = 0.890 ns ( 53.52 % )
                Info: Total interconnect delay = 0.773 ns ( 46.48 % )
        Info: + Micro clock to output delay of source is 0.335 ns
        Info: + Micro setup delay of destination is 0.198 ns
Info: tsu for register dout10[3]~reg0 (data pin = RE, clock pin = clk) is 5.969 ns
    Info: + Longest pin to register delay is 7.434 ns
        Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_30; Fanout = 1; PIN Node = 'RE'
        Info: 2: + IC(4.296 ns) + CELL(0.358 ns) = 5.894 ns; Loc. = LC3_7_E1; Fanout = 8; COMB Node = 'dout10[3]~8'
        Info: 3: + IC(1.031 ns) + CELL(0.509 ns) = 7.434 ns; Loc. = LC6_6_E1; Fanout = 2; REG Node = 'dout10[3]~reg0'
        Info: Total cell delay = 2.107 ns ( 28.34 % )
        Info: Total interconnect delay = 5.327 ns ( 71.66 % )
    Info: + Micro setup delay of destination is 0.198 ns
    Info: - Shortest clock path from clock clk to destination register is 1.663 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC6_6_E1; Fanout = 2; REG Node = 'dout10[3]~reg0'
        Info: Total cell delay = 0.890 ns ( 53.52 % )
        Info: Total interconnect delay = 0.773 ns ( 46.48 % )
Info: tco from clock clk to destination pin dout10[0] through register dout10[0]~reg0 is 6.859 ns
    Info: + Longest clock path from clock clk to source register is 1.663 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC5_6_E1; Fanout = 2; REG Node = 'dout10[0]~reg0'
        Info: Total cell delay = 0.890 ns ( 53.52 % )
        Info: Total interconnect delay = 0.773 ns ( 46.48 % )
    Info: + Micro clock to output delay of source is 0.335 ns
    Info: + Longest register to pin delay is 4.861 ns
        Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC5_6_E1; Fanout = 2; REG Node = 'dout10[0]~reg0'
        Info: 2: + IC(2.290 ns) + CELL(2.410 ns) = 4.861 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'dout10[0]'
        Info: Total cell delay = 2.571 ns ( 52.89 % )
        Info: Total interconnect delay = 2.290 ns ( 47.11 % )
Info: th for register dout10[0]~reg0 (data pin = din10[0], clock pin = clk) is -3.012 ns
    Info: + Longest clock path from clock clk to destination register is 1.663 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC5_6_E1; Fanout = 2; REG Node = 'dout10[0]~reg0'
        Info: Total cell delay = 0.890 ns ( 53.52 % )
        Info: Total interconnect delay = 0.773 ns ( 46.48 % )
    Info: + Micro hold delay of destination is 0.364 ns
    Info: - Shortest pin to register delay is 5.039 ns
        Info: 1: + IC(0.000 ns) + CELL(1.310 ns) = 1.310 ns; Loc. = PIN_64; Fanout = 2; PIN Node = 'din10[0]'
        Info: 2: + IC(3.650 ns) + CELL(0.079 ns) = 5.039 ns; Loc. = LC5_6_E1; Fanout = 2; REG Node = 'dout10[0]~reg0'
        Info: Total cell delay = 1.389 ns ( 27.56 % )
        Info: Total interconnect delay = 3.650 ns ( 72.44 % )
Info: Minimum tco from clock clk to destination pin result through register result~reg0 is 5.627 ns
    Info: + Shortest clock path from clock clk to source register is 1.663 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC2_6_E1; Fanout = 1; REG Node = 'result~reg0'
        Info: Total cell delay = 0.890 ns ( 53.52 % )
        Info: Total interconnect delay = 0.773 ns ( 46.48 % )
    Info: + Micro clock to output delay of source is 0.335 ns
    Info: + Shortest register to pin delay is 3.629 ns
        Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC2_6_E1; Fanout = 1; REG Node = 'result~reg0'
        Info: 2: + IC(1.058 ns) + CELL(2.410 ns) = 3.629 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'result'
        Info: Total cell delay = 2.571 ns ( 70.85 % )
        Info: Total interconnect delay = 1.058 ns ( 29.15 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Oct 31 05:27:41 2004
    Info: Elapsed time: 00:00:01