reg_comp.vhd

4X4 KEYPAD 的密码比较模块

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-- Copyright (C) 1991-2004 Altera Corporation
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-- Generated by Quartus II Version 4.1 (Build Build 208 09/10/2004)
-- Created on Sun Oct 24 17:46:05 2004

-- 6 register will store 6 numbers;
-- each register will compare the storeage with the number being selected when
-- it is in the state of compare, and feedback a result of comparation;
-- this is only one register;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY reg_comp IS
	PORT
	(
	   signal din10,din1: in std_logic_vector (3 downto 0);
	   signal read_comp,clk,RE,reset:  in std_logic;
	   signal result:     out std_logic;
	   signal dout10: out std_logic_vector (3 downto 0);
       signal dout1: out std_logic_vector (3 downto 0)
	);
END reg_comp;

ARCHITECTURE reg_comp_architecture OF reg_comp IS
signal temp_din10,temp_din1: std_logic_vector ( 3 downto 0);
BEGIN
process(clk,RE,din10,din1,read_comp,reset)
begin
    if reset='1' then
      if (clk'event and clk='1') then
           if read_comp='1' then   -- state of read a number
              if (RE='0') then
                 temp_din10<=din10;
                 temp_din1<=din1;
                 dout10<=din10;
                 dout1<=din1;
              end if;
           end if;
           if read_comp='0' then  -- state of comparation
             if (din1=temp_din1 and din10=temp_din10) then
                   result<='1'; -- result is 1 when the number being selected
                                -- is the same as it be stored in this register;
             else 
                   result<='0';
             end if;
           end if;
      end if;
    elsif reset='0' then -- set to initial
          dout1<="0000";
          dout10<="0000";
          result<='0';
          temp_din10<="0000";
          temp_din1<="0000";
   end if;          
end process;
END reg_comp_architecture;