top_func.v

DDR（双速率）SDRAM控制器参考设计

   input [7:0] ddr_write_en;
   input ddr_dqs_t;
   input [`ENABLE_MSB:0] ddr_read_en;
   input u_data_valid_en;
   input clk2x, clk, clk270, lac_clk_in;	
   input [1:0] cas_lat_half;
   input burst_8;
   inout [`DDR_DATA_MSB:0] ddr_dq;
   output [`U_DATA_MSB:0] u_data_o;
   output [1:0]ddr_dqs;
   output u_data_valid;

   //GND   global_gnd (G0);
   //VCC   global_vcc (V1);

   wire G0, V1;
   assign G0=1'b0;
   assign V1=1'b1;
   

/***************
* Write cycle *
***************/
   /**************************************
    * pipeline/duplicate control signals *
    **************************************/
   //pipeline ddr_write_en
   reg 			     ddr_write_en_P1;
   always @(posedge clk) begin
      ddr_write_en_P1 <= ddr_write_en;
   end

   /*******************
    * generate ddr_dq *
    *******************/

   //use shift register LUTs to delay input data for 5 clk cycles
   //SRL have show clk2out delay, always use ff after SRL to get better timing
   wire [`U_DATA_MSB:0] write_data;
   wire [`U_DATA_MSB:0] u_data_i_P5;

   data_dly u_data_dly (.I(u_data_i), .O(write_data), .CLK(clk));
         
   //instantiate DDR IOB flip-flop  
   wire [`DDR_DATA_MSB:0]     ddr_dq_o;

   ddr_iob_ff u_ddr_iob_ff (.D(write_data),.CLK(clk),.Q(ddr_dq_o),.CE(ddr_write_en_P1),.R(1'b0),.S(1'b0));
   
   //generate tristate signal for ddr_dq
   //ddr_dq_t f/f should be in IOB

   reg [`DDR_DATA_MSB:0]     ddr_dq_t;
   always @(negedge clk) begin
      ddr_dq_t   <= #18 {16{~ddr_write_en}}; //simulate IOB clk-2-out delay
   end 

   //IO buffers to get out of FPGA

   wire [`DDR_DATA_MSB:0]    ddr_dq_i;
   wire [15:0] #18 ddr_dq_o_wire =  ddr_dq_o; //simulates IOB clk-to-out delay
   ddr_dq_io_16 ddr_dq_io (.ddr_dq_i(ddr_dq_i), .ddr_dq(ddr_dq), .ddr_dq_o(ddr_dq_o_wire), .ddr_dq_t(ddr_dq_t));
 

   /****************
    * generate dqs *
    ****************/
   wire [1:0] 	  ddr_dqs_o_reg;
   reg [1:0] 	  ddr_dqs_t_reg;
   reg 		  ddr_dqs_t_P1,ddr_dqs_t_P2 ;
   //tristate signal for dqs
   always @(posedge clk) begin
      ddr_dqs_t_P1 <= ddr_dqs_t;
      ddr_dqs_t_P2 <= ddr_dqs_t_P1;
      ddr_dqs_t_reg <= {2{ddr_dqs_t_P1}};
   end
   
   //use DDR IOB flip-flop to generate DQS pulse (select b/t 1 & 0)
   //DQS is generated by clk270 to center the edges around data
   FDDRRSE ff_dqs0 (.D0(V1),.C0(clk270),.D1(G0),.C1(~clk270),.Q(ddr_dqs_o_reg[0]),.CE(V1),.R(ddr_dqs_t_P2),.S(G0));
   FDDRRSE ff_dqs1 (.D0(V1),.C0(clk270),.D1(G0),.C1(~clk270),.Q(ddr_dqs_o_reg[1]),.CE(V1),.R(ddr_dqs_t_P2),.S(G0));

   wire [1:0] #18 ddr_dqs_o_wire =  ddr_dqs_o_reg; //simulate IOB clk-to-out delay
   OBUFT  ddr_dqs0 (.I(ddr_dqs_o_wire[0]), .O(ddr_dqs[0]), .T(ddr_dqs_t_reg[0]));
   OBUFT  ddr_dqs1 (.I(ddr_dqs_o_wire[1]), .O(ddr_dqs[1]), .T(ddr_dqs_t_reg[1]));

   
/**************
 * READ cycle *
 **************/

   //pipeline read control signals
   reg u_data_valid_en_P1, u_data_valid_en_P2, u_data_valid_en_P3, u_data_valid_en_P4;
   always @(posedge clk) begin
      u_data_valid_en_P1 <= u_data_valid_en;
      u_data_valid_en_P2 <= u_data_valid_en_P1;
      u_data_valid_en_P3 <= u_data_valid_en_P2;
      u_data_valid_en_P4 <= u_data_valid_en_P3;
   end
 
   // read in data
   reg  [`U_DATA_MSB:0]  u_data_o_20, u_data_o_20_tmp, u_data_o_20_tmp_P1, u_data_o_20_P1;
   reg  [`U_DATA_MSB:0]  u_data_o_25, u_data_o_25_tmp, u_data_o_25_P1;
   wire [`U_DATA_MSB:0] u_data_o;

   //CAS latency 2.5
   	always @(posedge clk) 
     if (ddr_read_en[0]) u_data_o_25_tmp[`U_DATA_MSB:`DDR_DATA_MSB+1] <= ddr_dq_i;
   
	always @(negedge clk) 
     if (ddr_read_en[1]) u_data_o_25_tmp[`DDR_DATA_MSB:0]  <= ddr_dq_i;
   
   	always @(posedge clk) u_data_o_25 <= u_data_o_25_tmp;

   // CAS latency 2
   	always @(negedge clk) 
     if (ddr_read_en[0]) u_data_o_20_tmp[`U_DATA_MSB:`DDR_DATA_MSB+1]  <= ddr_dq_i;
   
	always @(posedge clk) 
     if (ddr_read_en[1]) u_data_o_20_tmp[`DDR_DATA_MSB:0]  <= ddr_dq_i;
   
   always @(negedge clk) u_data_o_20_tmp_P1 <= u_data_o_20_tmp;
   
   always @(posedge clk) u_data_o_20 <= u_data_o_20_tmp_P1;

   assign u_data_o = cas_lat_half[0]? u_data_o_25 : u_data_o_20;
	  
  //generate u_data_valid   
   reg u_data_valid_20, u_data_valid_25;
   wire u_data_valid;
   
   always @(posedge clk)
     if (u_data_valid_en_P4 && u_data_valid_en_P1) u_data_valid_25 <= 1;
     else       u_data_valid_25 <= 0;
   
    always @(posedge clk)
      if (u_data_valid_en_P4 && u_data_valid_en_P1) u_data_valid_20 <= 1;
      else       u_data_valid_20 <= 0;

   assign u_data_valid = cas_lat_half[1] ? u_data_valid_25 : u_data_valid_20;
  
  
endmodule 

module data_dly( I, O, CLK);
   input [`U_DATA_MSB:0] I;
   input 		 CLK;
   output [`U_DATA_MSB:0] O;
   
   wire [`U_DATA_MSB:0]   srl_o;
   reg [`U_DATA_MSB:0] 	  O;

   SRL16 U0 (.Q(srl_o[0]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[0]), .CLK(CLK));
   SRL16 U1 (.Q(srl_o[1]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[1]), .CLK(CLK));
   SRL16 U2 (.Q(srl_o[2]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[2]), .CLK(CLK));
   SRL16 U3 (.Q(srl_o[3]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[3]), .CLK(CLK));
   SRL16 U4 (.Q(srl_o[4]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[4]), .CLK(CLK));
   SRL16 U5 (.Q(srl_o[5]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[5]), .CLK(CLK));
   SRL16 U6 (.Q(srl_o[6]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[6]), .CLK(CLK));
   SRL16 U7 (.Q(srl_o[7]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[7]), .CLK(CLK));
   SRL16 U8 (.Q(srl_o[8]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[8]), .CLK(CLK));
   SRL16 U9 (.Q(srl_o[9]),   .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[9]), .CLK(CLK));
   SRL16 U10 (.Q(srl_o[10]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[10]), .CLK(CLK));
   SRL16 U11 (.Q(srl_o[11]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[11]), .CLK(CLK));
   SRL16 U12 (.Q(srl_o[12]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[12]), .CLK(CLK));
   SRL16 U13 (.Q(srl_o[13]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[13]), .CLK(CLK));
   SRL16 U14 (.Q(srl_o[14]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[14]), .CLK(CLK));
   SRL16 U15 (.Q(srl_o[15]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[15]), .CLK(CLK));
   SRL16 U16 (.Q(srl_o[16]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[16]), .CLK(CLK));
   SRL16 U17 (.Q(srl_o[17]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[17]), .CLK(CLK));
   SRL16 U18 (.Q(srl_o[18]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[18]), .CLK(CLK));
   SRL16 U19 (.Q(srl_o[19]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[19]), .CLK(CLK));
   SRL16 U20 (.Q(srl_o[20]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[20]), .CLK(CLK));
   SRL16 U21 (.Q(srl_o[21]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[21]), .CLK(CLK));
   SRL16 U22 (.Q(srl_o[22]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[22]), .CLK(CLK));
   SRL16 U23 (.Q(srl_o[23]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[23]), .CLK(CLK));
   SRL16 U24 (.Q(srl_o[24]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[24]), .CLK(CLK));
   SRL16 U25 (.Q(srl_o[25]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[25]), .CLK(CLK));
   SRL16 U26 (.Q(srl_o[26]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[26]), .CLK(CLK));
   SRL16 U27 (.Q(srl_o[27]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[27]), .CLK(CLK));
   SRL16 U28 (.Q(srl_o[28]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[28]), .CLK(CLK));
   SRL16 U29 (.Q(srl_o[29]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[29]), .CLK(CLK));
   SRL16 U30 (.Q(srl_o[30]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[30]), .CLK(CLK));
   SRL16 U31 (.Q(srl_o[31]), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .D(I[31]), .CLK(CLK));
	     
   always @(posedge CLK) begin
      O <= srl_o;
   end
endmodule // data_dly

module ddr_iob_ff ( D, CLK, Q, CE, R, S);
   input [`U_DATA_MSB:0] D;
   input CLK;
   input CE, R, S;
   output [`DDR_DATA_MSB:0] Q;
   FDDRRSE ff_0  (.D0(D[0]), .C0(CLK),.D1(D[16]),.C1(~CLK),.Q(Q[0]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_1  (.D0(D[1]), .C0(CLK),.D1(D[17]),.C1(~CLK),.Q(Q[1]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_2  (.D0(D[2]), .C0(CLK),.D1(D[18]),.C1(~CLK),.Q(Q[2]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_3  (.D0(D[3]), .C0(CLK),.D1(D[19]),.C1(~CLK),.Q(Q[3]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_4  (.D0(D[4]), .C0(CLK),.D1(D[20]),.C1(~CLK),.Q(Q[4]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_5  (.D0(D[5]), .C0(CLK),.D1(D[21]),.C1(~CLK),.Q(Q[5]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_6  (.D0(D[6]), .C0(CLK),.D1(D[22]),.C1(~CLK),.Q(Q[6]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_7  (.D0(D[7]), .C0(CLK),.D1(D[23]),.C1(~CLK),.Q(Q[7]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_8  (.D0(D[8]), .C0(CLK),.D1(D[24]),.C1(~CLK),.Q(Q[8]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_9  (.D0(D[9]), .C0(CLK),.D1(D[25]),.C1(~CLK),.Q(Q[9]), .CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_10 (.D0(D[10]),.C0(CLK),.D1(D[26]),.C1(~CLK),.Q(Q[10]),.CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_11 (.D0(D[11]),.C0(CLK),.D1(D[27]),.C1(~CLK),.Q(Q[11]),.CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_12 (.D0(D[12]),.C0(CLK),.D1(D[28]),.C1(~CLK),.Q(Q[12]),.CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_13 (.D0(D[13]),.C0(CLK),.D1(D[29]),.C1(~CLK),.Q(Q[13]),.CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_14 (.D0(D[14]),.C0(CLK),.D1(D[30]),.C1(~CLK),.Q(Q[14]),.CE(CE),.R(1'b0),.S(1'b0));
   FDDRRSE ff_15 (.D0(D[15]),.C0(CLK),.D1(D[31]),.C1(~CLK),.Q(Q[15]),.CE(CE),.R(1'b0),.S(1'b0));

endmodule // ddr_iob_ff

module ddr_dq_io_16 (/*AUTOARG*/
   // Outputs
   ddr_dq_i, 
   // Inouts
   ddr_dq, 
   // Inputs
   ddr_dq_o, ddr_dq_t
   );
   inout  [`DDR_DATA_MSB:0]   ddr_dq;
   input  [`DDR_DATA_MSB:0]   ddr_dq_o;
   output [`DDR_DATA_MSB:0]   ddr_dq_i;
   input [`DDR_DATA_MSB:0]    ddr_dq_t;

   IOBUF  dq0  (.I(ddr_dq_o[0]), .IO(ddr_dq[0]), .O(ddr_dq_i[0]), .T(ddr_dq_t[0]));
   IOBUF  dq1  (.I(ddr_dq_o[1]), .IO(ddr_dq[1]), .O(ddr_dq_i[1]), .T(ddr_dq_t[1]));
   IOBUF  dq2  (.I(ddr_dq_o[2]), .IO(ddr_dq[2]), .O(ddr_dq_i[2]), .T(ddr_dq_t[2]));
   IOBUF  dq3  (.I(ddr_dq_o[3]), .IO(ddr_dq[3]), .O(ddr_dq_i[3]), .T(ddr_dq_t[3]));
   IOBUF  dq4  (.I(ddr_dq_o[4]), .IO(ddr_dq[4]), .O(ddr_dq_i[4]), .T(ddr_dq_t[4]));
   IOBUF  dq5  (.I(ddr_dq_o[5]), .IO(ddr_dq[5]), .O(ddr_dq_i[5]), .T(ddr_dq_t[5]));
   IOBUF  dq6  (.I(ddr_dq_o[6]), .IO(ddr_dq[6]), .O(ddr_dq_i[6]), .T(ddr_dq_t[6]));
   IOBUF  dq7  (.I(ddr_dq_o[7]), .IO(ddr_dq[7]), .O(ddr_dq_i[7]), .T(ddr_dq_t[7]));
   IOBUF  dq8  (.I(ddr_dq_o[8]), .IO(ddr_dq[8]), .O(ddr_dq_i[8]), .T(ddr_dq_t[8]));
   IOBUF  dq9  (.I(ddr_dq_o[9]), .IO(ddr_dq[9]), .O(ddr_dq_i[9]), .T(ddr_dq_t[9]));
   IOBUF  dq10 (.I(ddr_dq_o[10]),.IO(ddr_dq[10]),.O(ddr_dq_i[10]),.T(ddr_dq_t[10]));
   IOBUF  dq11 (.I(ddr_dq_o[11]),.IO(ddr_dq[11]),.O(ddr_dq_i[11]),.T(ddr_dq_t[11]));
   IOBUF  dq12 (.I(ddr_dq_o[12]),.IO(ddr_dq[12]),.O(ddr_dq_i[12]),.T(ddr_dq_t[12]));
   IOBUF  dq13 (.I(ddr_dq_o[13]),.IO(ddr_dq[13]),.O(ddr_dq_i[13]),.T(ddr_dq_t[13]));
   IOBUF  dq14 (.I(ddr_dq_o[14]),.IO(ddr_dq[14]),.O(ddr_dq_i[14]),.T(ddr_dq_t[14]));
   IOBUF  dq15 (.I(ddr_dq_o[15]),.IO(ddr_dq[15]),.O(ddr_dq_i[15]),.T(ddr_dq_t[15]));

endmodule // ddr_dq_io_16


module rcd_cntr (/*AUTOARG*/
   // Outputs
   rcd_end, 
   // Inputs
   clk, ld_rcd
   );
   output rcd_end;
   input  clk, ld_rcd;

   reg 	  rcd_end;
   always @ (posedge clk)       
   			rcd_end <= ~ld_rcd;

endmodule


module user_int (/*AUTOARG*/
   // Outputs
   sys_data_o, 
   sys_ref_ack, 
   sys_data_valid, 
   u_addr, 
   u_data_i, 
   u_cmd, 
   u_reset_n, 
   u_clk, 
   u_clk_fb, 
   // Inputs
   sys_addr, 
   sys_data_i, 
   sys_cmd, 
   sys_reset_n, 
   sys_clk, 
   sys_clk_fb, 
   u_data_o,
   u_ref_ack, 
   u_data_valid, 
   fpga_clk
   );

   input [`SYS_ADDR_MSB:0]  sys_addr;
   input [`SYS_DATA_MSB:0]  sys_data_i;
   output [`SYS_DATA_MSB:0] sys_data_o;
   input [7:1] sys_cmd;
   input sys_reset_n;
   input sys_clk;
   output sys_ref_ack; 		    
   input sys_clk_fb;
   output sys_data_valid;
   
   output [`U_ADDR_MSB:0] u_addr;
   output [`U_DATA_MSB:0] u_data_i;
   input [`U_DATA_MSB:0]  u_data_o;
   output [7:1] u_cmd;
   output u_reset_n;
   output u_clk;
   input u_ref_ack; 		    
   output u_clk_fb;
   input u_data_valid;
   input fpga_clk;

   wire [`DDR_ADDR_MSB:0] ddr_ad;
   wire [`DDR_DATA_MSB:0] ddr_dq;
   wire [1:0] ddr_dm;
   wire [1:0] ddr_ba; 
   wire [1:0] ddr_dqs;
   
   wire [`SYS_ADDR_MSB:0] sys_addr_pad;
   wire [`SYS_DATA_MSB:0] sys_data_i_pad;
   reg [`SYS_DATA_MSB:0]  sys_data_o_pad;
   wire [7:1] sys_cmd_pad;
   wire sys_reset_n_pad;
   reg 	sys_data_valid_pad;
   
   //register all system inputs to in IOBs, except clk signals
   reg [`U_ADDR_MSB:0] u_addr;
   reg [`U_DATA_MSB:0] u_data_i;
   reg [7:1] u_cmd;
   reg u_reset_n;
   wire [`SYS_DATA_MSB:0] sys_data_o;
   wire sys_data_valid;
   
   always @(posedge fpga_clk) begin      
      u_addr <= sys_addr_pad;
      u_data_i <= sys_data_i_pad;
      u_cmd <= sys_cmd_pad;
      u_reset_n <= sys_reset_n_pad;
      sys_data_o_pad <= u_data_o;
      sys_data_valid_pad <= u_data_valid;
   end
   wire 		   u_clk = sys_clk;
   wire 		   sys_ref_ack_pad = u_ref_ack;
   wire 		   u_clk_fb = sys_clk_fb;


   //instantiate IO buffers
   IBUF  U_a0 (.I(sys_addr[0]), .O(sys_addr_pad[0]));
   IBUF  U_a1 (.I(sys_addr[1]), .O(sys_addr_pad[1]));
   IBUF  U_a2 (.I(sys_addr[2]), .O(sys_addr_pad[2]));
   IBUF  U_a3 (.I(sys_addr[3]), .O(sys_addr_pad[3]));
   IBUF  U_a4 (.I(sys_addr[4]), .O(sys_addr_pad[4]));
   IBUF  U_a5 (.I(sys_addr[5]), .O(sys_addr_pad[5]));
   IBUF  U_a6 (.I(sys_addr[6]), .O(sys_addr_pad[6]));
   IBUF  U_a7 (.I(sys_addr[7]), .O(sys_addr_pad[7]));
   IBUF  U_a8 (.I(sys_addr[8]), .O(sys_addr_pad[8]));
   IBUF  U_a9 (.I(sys_addr[9]), .O(sys_addr_pad[9]));
   IBUF  U_a10 (.I(sys_addr[10]), .O(sys_addr_pad[10]));
   IBUF  U_a11 (.I(sys_addr[11]), .O(sys_addr_pad[11]));
   IBUF  U_a12 (.I(sys_addr[12]), .O(sys_addr_pad[12]));
   IBUF  U_a13 (.I(sys_addr[13]), .O(sys_addr_pad[13]));
   IBUF  U_a14 (.I(sys_addr[14]), .O(sys_addr_pad[14]));
   IBUF  U_a15 (.I(sys_addr[15]), .O(sys_addr_pad[15]));
   IBUF  U_a16 (.I(sys_addr[16]), .O(sys_addr_pad[16]));
   IBUF  U_a17 (.I(sys_addr[17]), .O(sys_addr_pad[17]));
   IBUF  U_a18 (.I(sys_addr[18]), .O(sys_addr_pad[18]));
   IBUF  U_a19 (.I(sys_addr[19]), .O(sys_addr_pad[19]));
   IBUF  U_a20 (.I(sys_addr[20]), .O(sys_addr_pad[20]));
   IBUF  U_a21 (.I(sys_addr[21]), .O(sys_addr_pad[21]));


   IBUF  U_di0 (.I(sys_data_i[0]), .O(sys_data_i_pad[0]));
   IBUF  U_di1 (.I(sys_data_i[1]), .O(sys_data_i_pad[1]));
   IBUF  U_di2 (.I(sys_data_i[2]), .O(sys_data_i_pad[2]));
   IBUF  U_di3 (.I(sys_data_i[3]), .O(sys_data_i_pad[3]));
   IBUF  U_di4 (.I(sys_data_i[4]), .O(sys_data_i_pad[4]));
   IBUF  U_di5 (.I(sys_data_i[5]), .O(sys_data_i_pad[5]));
   IBUF  U_di6 (.I(sys_data_i[6]), .O(sys_data_i_pad[6]));
   IBUF  U_di7 (.I(sys_data_i[7]), .O(sys_data_i_pad[7]));
   IBUF  U_di8 (.I(sys_data_i[8]), .O(sys_data_i_pad[8]));
   IBUF  U_di9 (.I(sys_data_i[9]), .O(sys_data_i_pad[9]));
   IBUF  U_di10 (.I(sys_data_i[10]), .O(sys_data_i_pad[10]));
   IBUF  U_di11 (.I(sys_data_i[11]), .O(sys_data_i_pad[11]));
   IBUF  U_di12 (.I(sys_data_i[12]), .O(sys_data_i_pad[12]));
   IBUF  U_di13 (.I(sys_data_i[13]), .O(sys_data_i_pad[13]));
   IBUF  U_di14 (.I(sys_data_i[14]), .O(sys_data_i_pad[14]));
   IBUF  U_di15 (.I(sys_data_i[15]), .O(sys_data_i_pad[15]));
   IBUF  U_di16 (.I(sys_data_i[16]), .O(sys_data_i_pad[16]));
   IBUF  U_di17 (.I(sys_data_i[17]), .O(sys_data_i_pad[17]));
   IBUF  U_di18 (.I(sys_data_i[18]), .O(sys_data_i_pad[18]));
   IBUF  U_di19 (.I(sys_data_i[19]), .O(sys_data_i_pad[19]));
   IBUF  U_di20 (.I(sys_data_i[20]), .O(sys_data_i_pad[20]));
   IBUF  U_di21 (.I(sys_data_i[21]), .O(sys_data_i_pad[21]));
   IBUF  U_di22 (.I(sys_data_i[22]), .O(sys_data_i_pad[22]));
   IBUF  U_di23 (.I(sys_data_i[23]), .O(sys_data_i_pad[23]));
   IBUF  U_di24 (.I(sys_data_i[24]), .O(sys_data_i_pad[24]));
   IBUF  U_di25 (.I(sys_data_i[25]), .O(sys_data_i_pad[25]));
   IBUF  U_di26 (.I(sys_data_i[26]), .O(sys_data_i_pad[26]));
   IBUF  U_di27 (.I(sys_data_i[27]), .O(sys_data_i_pad[27]));
   IBUF  U_di28 (.I(sys_data_i[28]), .O(sys_data_i_pad[28]));
   IBUF  U_di29 (.I(sys_data_i[29]), .O(sys_data_i_pad[29]));
   IBUF  U_di30 (.I(sys_data_i[30]), .O(sys_data_i_pad[30]));
   IBUF  U_di31 (.I(sys_data_i[31]), .O(sys_data_i_pad[31]));


   IBUF  U_cmd1 (.I(sys_cmd[1]), .O(sys_cmd_pad[1]));
   IBUF  U_cmd2 (.I(sys_cmd[2]), .O(sys_cmd_pad[2]));
   IBUF  U_cmd3 (.I(sys_cmd[3]), .O(sys_cmd_pad[3]));
   IBUF  U_cmd4 (.I(sys_cmd[4]), .O(sys_cmd_pad[4]));
   IBUF  U_cmd5 (.I(sys_cmd[5]), .O(sys_cmd_pad[5]));
   IBUF  U_cmd6 (.I(sys_cmd[6]), .O(sys_cmd_pad[6]));
   IBUF  U_cmd7 (.I(sys_cmd[7]), .O(sys_cmd_pad[7]));

   IBUF  U_reset (.I(sys_reset_n), .O(sys_reset_n_pad));

   OBUF  U_data_valid (.O(sys_data_valid),  .I(sys_data_valid_pad));
   OBUF  U_ref_ack (.O(sys_ref_ack),  .I(sys_ref_ack_pad));
 
   OBUF  U_do0  (.O(sys_data_o[0]),  .I(sys_data_o_pad[0]));
   OBUF  U_do1  (.O(sys_data_o[1]),  .I(sys_data_o_pad[1]));
   OBUF  U_do2  (.O(sys_data_o[2]),  .I(sys_data_o_pad[2]));
   OBUF  U_do3  (.O(sys_data_o[3]),  .I(sys_data_o_pad[3]));
   OBUF  U_do4  (.O(sys_data_o[4]),  .I(sys_data_o_pad[4]));
   OBUF  U_do5  (.O(sys_data_o[5]),  .I(sys_data_o_pad[5]));
   OBUF  U_do6  (.O(sys_data_o[6]),  .I(sys_data_o_pad[6]));
   OBUF  U_do7  (.O(sys_data_o[7]),  .I(sys_data_o_pad[7]));
   OBUF  U_do8  (.O(sys_data_o[8]),  .I(sys_data_o_pad[8]));
   OBUF  U_do9  (.O(sys_data_o[9]),  .I(sys_data_o_pad[9]));
   OBUF  U_do10 (.O(sys_data_o[10]), .I(sys_data_o_pad[10]));
   OBUF  U_do11 (.O(sys_data_o[11]), .I(sys_data_o_pad[11]));
   OBUF  U_do12 (.O(sys_data_o[12]), .I(sys_data_o_pad[12]));
   OBUF  U_do13 (.O(sys_data_o[13]), .I(sys_data_o_pad[13]));
   OBUF  U_do14 (.O(sys_data_o[14]), .I(sys_data_o_pad[14]));
   OBUF  U_do15 (.O(sys_data_o[15]), .I(sys_data_o_pad[15]));
   OBUF  U_do16 (.O(sys_data_o[16]), .I(sys_data_o_pad[16]));
   OBUF  U_do17 (.O(sys_data_o[17]), .I(sys_data_o_pad[17]));
   OBUF  U_do18 (.O(sys_data_o[18]), .I(sys_data_o_pad[18]));
   OBUF  U_do19 (.O(sys_data_o[19]), .I(sys_data_o_pad[19]));
   OBUF  U_do20 (.O(sys_data_o[20]), .I(sys_data_o_pad[20]));
   OBUF  U_do21 (.O(sys_data_o[21]), .I(sys_data_o_pad[21]));
   OBUF  U_do22 (.O(sys_data_o[22]), .I(sys_data_o_pad[22]));
   OBUF  U_do23 (.O(sys_data_o[23]), .I(sys_data_o_pad[23]));
   OBUF  U_do24 (.O(sys_data_o[24]), .I(sys_data_o_pad[24]));
   OBUF  U_do25 (.O(sys_data_o[25]), .I(sys_data_o_pad[25]));
   OBUF  U_do26 (.O(sys_data_o[26]), .I(sys_data_o_pad[26]));
   OBUF  U_do27 (.O(sys_data_o[27]), .I(sys_data_o_pad[27]));
   OBUF  U_do28 (.O(sys_data_o[28]), .I(sys_data_o_pad[28]));
   OBUF  U_do29 (.O(sys_data_o[29]), .I(sys_data_o_pad[29]));
   OBUF  U_do30 (.O(sys_data_o[30]), .I(sys_data_o_pad[30]));
   OBUF  U_do31 (.O(sys_data_o[31]), .I(sys_data_o_pad[31]));
		   
endmodule // top