top_func.v

DDR（双速率）SDRAM控制器参考设计

/******************************************************************************
 *
 *    File Name:  top.v
 *      Version:  1.0
 *         Date:  Jan 12, 2001
 * 
 *  Description:  instantiate ddr_ctrl and a dummy user_int module.
 *                In order to place and route the ddr_ctrl module, we need to
 *                connect all user interface signals.  The user_int module simply
 *                connects all user signals to IOs.  
 * 
 *                The user should replace user_int module with their own interface.
 * 
 * 
 *       Author:  Jennnifer Tran and Ratima Kataria
 *      Company:  Xilinx
 *
 *                Copyright (c) 1999 Xilinx, Inc.
 *                All rights reserved
 *
 *    DDR SDRAM:  64M (1M x 16Bit x 4Bank)
 * 
 *   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
 *                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
 *                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
 *                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
 *
 ******************************************************************************/
`timescale 100ps / 10ps

`define T_RCD 2   //ras to cas delay, for -8 SDRAM, we need 3 clock cycles for t_rcd

`define DDR_ADDR_MSB           11
`define DDR_DATA_MSB           15
`define SYS_ADDR_MSB           21
`define SYS_DATA_MSB           31
`define U_ADDR_MSB             21
`define U_DATA_MSB             31
`define ROW_ADDR_MSB           11
`define COL_ADDR_MSB           	7
`define ENABLE_MSB           	3

//system commands: sys_cmd[7:1]
`define sys_nop                7'b0000001
`define sys_load_mr            7'b0000010
`define sys_read               7'b0000100
`define sys_write              7'b0001000
`define sys_precharge          7'b0010000
`define sys_refresh            7'b0100000
`define sys_burst_stop         7'b1000000

`define SYS_NOP                1
`define SYS_LOAD_MR            2
`define SYS_READ               3
`define SYS_WRITE              4
`define SYS_PRECHARGE          5
`define SYS_REFRESH            6
`define SYS_BURST_STOP         7

   //controller states
`define CTLR_IDLE              1
`define CTLR_REFRESH           2
`define CTLR_PRECHARGE         3
`define CTLR_LOAD_MR           4
`define CTLR_ACT               5
`define CTLR_ACT_WAIT          6               
`define CTLR_READ              7
`define CTLR_WRITE             8
`define CTLR_READ_WAIT         9
`define CTLR_READ_DATA         10
`define CTLR_WRITE_DATA        11

   //DDR commands
`define DDR_LOAD_MR            3'b000
`define DDR_AUTO_REFRESH       3'b001
`define DDR_PRECHARGE          3'b010
`define DDR_ACT                3'b011
`define DDR_WRITEA             3'b100
`define DDR_READA              3'b101
`define DDR_BURST_STOP         3'b110
`define DDR_NOP                3'b111


module top (/*AUTOARG*/
   // Outputs
   ddr_ad, 
   ddr_dm, 
   ddr_ba, 
   ddr_rasb, 
   ddr_casb, 
   ddr_web, 
   ddr_clk, 
   ddr_clkb, 
   ddr_dqs, 
   ddr_csb, 
   ddr_cke, 
   sys_data_o, 
   sys_ref_ack, 
   sys_data_valid, 
   // Inouts
   ddr_dq, 
   // Inputs
   sys_addr, 
   sys_data_i, 
   sys_cmd, 
   sys_reset_n, 
   sys_clk, 
   sys_clk_fb
   );

   output [`DDR_ADDR_MSB:0] ddr_ad;
   inout [`DDR_DATA_MSB:0]  ddr_dq;   
   output [1:0] ddr_dm;
   output [1:0] ddr_ba; 
   output ddr_rasb, ddr_casb, ddr_web;
   output ddr_clk, ddr_clkb;
   output [1:0] ddr_dqs;
   output ddr_csb, ddr_cke;
   
   input [`SYS_ADDR_MSB:0]  sys_addr;
   input [`SYS_DATA_MSB:0]  sys_data_i;
   output [`SYS_DATA_MSB:0] sys_data_o;
   input [7:1] sys_cmd;
   input sys_reset_n;
   input sys_clk;
   output sys_ref_ack; 		    
   input sys_clk_fb;
   output sys_data_valid;

   wire [`U_ADDR_MSB:0] u_addr;
   wire [`U_DATA_MSB:0] u_data_i;
   wire [`U_DATA_MSB:0] u_data_o;
   wire [7:1] u_cmd;

	   ddr_ctlr I_ddr_ctlr (.ddr_ad(ddr_ad), 
	   						.ddr_dm(ddr_dm), 
							.ddr_ba(ddr_ba), 
					      .ddr_rasb(ddr_rasb), 
						  .ddr_casb(ddr_casb), 
						  .ddr_web(ddr_web), 
					      .ddr_clk(ddr_clk), 
						  .ddr_clkb(ddr_clkb), 
						  .ddr_dqs(ddr_dqs), 
					      .ddr_csb(ddr_csb), 
						  .ddr_cke(ddr_cke),
						  .ddr_dq(ddr_dq),
						  .u_addr(u_addr),
						  .u_cmd(u_cmd), 
						  .u_reset_n(u_reset_n), 
						  .u_data_o(u_data_o),
						  .u_data_i(u_data_i),
						  .u_ref_ack(u_ref_ack),
						  .u_data_valid(u_data_valid),
						  .u_clk(u_clk), 
						  .u_clk_fb(u_clk_fb),
						  .fpga_clk(fpga_clk));
   
   user_int I_user_int (.sys_data_o(sys_data_o),
   						.sys_ref_ack(sys_ref_ack), 
						.sys_data_valid(sys_data_valid),
					 	.u_addr(u_addr), 
						.u_data_i(u_data_i),
					 	.u_cmd(u_cmd), 
						.u_reset_n(u_reset_n),
					 	.u_clk(u_clk), 
						.u_clk_fb(u_clk_fb),
						.sys_addr(sys_addr),
					 	.sys_data_i(sys_data_i), 
						.sys_cmd(sys_cmd),
					 	.sys_reset_n(sys_reset_n), 
						.sys_clk(sys_clk),
					 	.sys_clk_fb(sys_clk_fb), 
						.u_data_o(u_data_o), 
						.u_ref_ack(u_ref_ack),
					 	.u_data_valid(u_data_valid),
				  		.fpga_clk(fpga_clk));
   
endmodule // top


module ddr_ctlr (/*AUTOARG*/
   // Outputs
   ddr_ad,
   ddr_dm,
   ddr_ba,
   ddr_rasb,
   ddr_casb,
   ddr_web,
   ddr_clk, 
   ddr_clkb,
   ddr_dqs,
   ddr_csb,
   ddr_cke,
   u_data_o,
   u_ref_ack, 
   u_data_valid,
   fpga_clk, 
   // Inouts
   ddr_dq, 
   // Inputs
   u_addr,
   u_data_i,
   u_cmd,
   u_reset_n,
   u_clk,
   u_clk_fb
   );

   output [`DDR_ADDR_MSB:0] ddr_ad;
   inout [`DDR_DATA_MSB:0]  ddr_dq;   
   output [1:0] ddr_dm;
   output [1:0] ddr_ba; 
   output ddr_rasb, ddr_casb, ddr_web;
   output ddr_clk, ddr_clkb;
   output [1:0]ddr_dqs;
   output ddr_csb, ddr_cke;
   
   input [`U_ADDR_MSB:0]  u_addr;
   input [`U_DATA_MSB:0]  u_data_i;
   output [`U_DATA_MSB:0] u_data_o;
   input [7:1]u_cmd;
   input u_reset_n;
   input u_clk;
   output u_ref_ack; 		    
   input u_clk_fb;
   output u_data_valid;
   
   output  fpga_clk;

   wire [1:0] cas_lat_half;
   wire [1:0] ddr_burst_length;
   wire [2:0] ddr_cas_latency;
   wire [1:0] cas_lat_max;
   wire dlls_locked;		    
   wire reset = ~(dlls_locked & u_reset_n);
   wire [7:0] ddr_write_en;
   wire [`ENABLE_MSB:0] ddr_read_en; 		    
   
   //fanout reset to reduce net delay
   reg 	ctlr_reset1, ctlr_reset2, ctlr_reset3;
   reg 	addr_reset1, addr_reset2;
   always @(posedge fpga_clk) begin
      ctlr_reset1 <= reset;
      ctlr_reset2 <= reset;
      ctlr_reset3 <= reset;
      addr_reset1 <= reset;
      addr_reset2 <= reset; 
   end
   
   /*********************************************************\
    *       Instantiation of sub modules.                   *
    *                                                       *
   \********************************************************/   
   clk_dlls clk_dlls (	.ddr_clk_out(ddr_clk), 
   						.ddr_clk180_out(ddr_clkb),
		     				.fpga_clk2x_out(fpga_clk2x),
		   				.fpga_clk_out(fpga_clk),
		      			.fpga_clk270_out(fpga_clk270),
					//		.fpga_clk90_out(fpga_clk90),
		      			.dlls_locked_out(dlls_locked),
		   				.sys_clk_in(u_clk), 
		      			.sys_clk_fb_in(u_clk_fb),
		   				.fpga_lac_clk_out(fpga_lac_clk), 
		      			.reset_in(1'b0), 
			  				.fpga_lac_clk90_out(fpga_lac_clk90));
   
   data_path data_path (.u_data_o(u_data_o), 
   						.ddr_dqs(ddr_dqs), 
							.u_data_valid(u_data_valid), 
							.burst_8(burst_8),
							.ddr_dq(ddr_dq), 
							.u_data_i(u_data_i), 
							.ddr_dqs_t(ddr_dqs_t), 
							.u_data_valid_en(u_data_valid_en),
							.ddr_write_en(ddr_write_en), 
							.ddr_read_en(ddr_read_en), 
							.clk2x(fpga_clk2x), 
							.clk(fpga_clk),
						 	.clk270(fpga_clk270),
							.lac_clk_in(fpga_lac_clk), 
							.cas_lat_half(cas_lat_half));

   addr_latch addr_latch(	.burst_2(burst_2), 
   							.burst_8(burst_8), 
								.cas_lat_max(cas_lat_max), 
								.cas_lat_half(cas_lat_half),
								.ddr_ad(ddr_ad), 
								.ddr_ba(ddr_ba), 
								.u_addr(u_addr), 
								.row_addr(row_addr),
							  	.mrs_addr(mrs_addr),
							  	.clk(fpga_clk), 
								.reset2(addr_reset2),
							  	.reset1(addr_reset1));

   controller controller (	.ddr_rasb(ddr_rasb), 
   							.ddr_casb(ddr_casb), 
							  .ddr_web(ddr_web), 
							  .ld_burst(ld_burst), 
							  .ld_rcd(ld_rcd), 
							  .ld_cas_lat(ld_cas_lat), 
							  .u_ref_ack(u_ref_ack), 
							  .ddr_read_en(ddr_read_en), 
							  .ddr_dqs_t(ddr_dqs_t), 
							  .u_data_valid_en(u_data_valid_en),
							  .ddr_write_en(ddr_write_en),
							  .mrs_addr(mrs_addr), 
							  .row_addr(row_addr), 
							  .burst_2(burst_2), 
							  .burst_8(burst_8),
							  .u_cmd(u_cmd), 
							  .cntlr_reset1(ctlr_reset1), 
							  .cntlr_reset2(ctlr_reset2), 
							  .cntlr_reset3(ctlr_reset3),
							  .clk2x(fpga_clk2x), 
							  .lac_clk_in(fpga_lac_clk90), 
							  .clk(fpga_clk), 
							  .burst_end(burst_end), 
							  .cas_lat_end(cas_lat_end), 
							  .rcd_end(rcd_end)
							//  .clk90(fpga_clk90)
							   );
    
   brst_cntr brst_cntr   (.brst_end(burst_end),
								  .clk(fpga_clk), 
								  .ld_brst(ld_burst));

   cslt_cntr cslt_cntr   (.cslt_end(cas_lat_end), 
				   			  .cslt_max(cas_lat_max),
								  .cas_lat_half(cas_lat_half[1]), 
								  .clk(fpga_clk), 
								  .clk2x(fpga_clk2x), 
								  .ld_cslt(ld_cas_lat));

   rcd_cntr rcd_cntr     (.rcd_end(rcd_end),
								  .clk(fpga_clk), 
								  .ld_rcd(ld_rcd));

   //interface to DDR signals
   //all inputs/outputs use SSTL2_II
   OBUF O_ddr_dqm0 (.O(ddr_dm[0]), .I(1'b0));
   OBUF O_ddr_dqm1 (.O(ddr_dm[1]), .I(1'b0));
   OBUF O_ddr_cke  (.O(ddr_cke), .I(1'b1));
   OBUF O_ddr_csb  (.O(ddr_csb), .I(1'b0));  
   
endmodule

module addr_latch(/*AUTOARG*/
   // Outputs
   ddr_ad, 
   cas_lat_max, 
   cas_lat_half, 
   ddr_ba, burst_2, 
   burst_8, 
   // Inputs
   u_addr, 
   row_addr, 
   clk, 
   reset1, 
   reset2, 
   mrs_addr
   );
   
   output [`DDR_ADDR_MSB:0] ddr_ad;
   output [1:0] cas_lat_max;
   output [1:0] cas_lat_half;
   output [1:0] ddr_ba;
   output burst_2, burst_8;
   
   input [`U_ADDR_MSB:0] u_addr;
   input 		    row_addr;
   input 		    clk;
   input 		    reset1, reset2;
   input 		    mrs_addr;
   
   
   reg [1:0] ddr_ba_o, ddr_ba_o_P1;
   reg [`DDR_ADDR_MSB:0] ddr_ad_o, ddr_ad_o_P1;
   reg [1:0] next_cas_lat_max, cas_lat_max;
   reg 	next_cas_lat_half;
   reg [1:0] cas_lat_half;
   wire [1:0] ddr_burst_length = u_addr[1:0];
   wire [2:0] ddr_cas_latency = u_addr[6:4];
   
   reg 	burst_2, burst_8;
   reg 	next_burst_2, next_burst_8;
   
   //decode burst length
   always @(ddr_burst_length) begin
      case (ddr_burst_length) 
	  2'b01:   begin 
	  				next_burst_2 = 1; 
	  				next_burst_8 = 0; 
				end
	  2'b10:   begin 
			  		next_burst_2 = 0; 
			  		next_burst_8 = 0; 
			  end 
	  default: begin 
				  next_burst_2 = 0; 
				  next_burst_8 = 1; 
			  end 
      endcase 
   end // always @ (ddr_burst_length) 

//   assign next_burst_2 = (ddr_burst_length == 2'b01) ? (1'b1) : (1'b0);
//   assign next_burst_8 = ((ddr_burst_length == 2'b01) || (ddr_burst_length == 2'b10)) ? (1'b0) : (1'b1);

   
   //generate cas_latency_max, cas_lat_half
   always @(ddr_cas_latency)
     case (ddr_cas_latency) 
       3'b011:  begin
		  			next_cas_lat_max = 2'b10; //cas_lat = 3
		  			next_cas_lat_half = 1'b0;
       			end
       3'b101:  begin
				  next_cas_lat_max = 2'b00; //cas_lat = 1.5
				  next_cas_lat_half = 1'b1;
			    end
       3'b110:  begin
				  next_cas_lat_max = 2'b01; //cas_lat = 2.5
				  next_cas_lat_half = 1'b1;
			    end
       default: begin
				  next_cas_lat_max = 2'b01; //cas_lat = 2
				  next_cas_lat_half = 1'b0;
			    end
     endcase 

   //generate address & ba
   //address & ba are generated on negative edge of clk to meet DDR hold time
   //ba is always on u_addr[21:20]
   //Mode register values are on u_addr[8:0]
   //for READ/WRITE:row addr are on u_addr[19:8]
   //               col addr are on u_addr[7:0], A10=1:auto_precharge
   //for precharge: A10=1:all banks (for mt46v2m32, A8 needs to be 1)
   always @(negedge clk) begin
      ddr_ba_o <= u_addr[21:20];
      if (mrs_addr)
		ddr_ad_o <= {3'b000,u_addr[8:0]};  
      else if (row_addr)
		ddr_ad_o <= u_addr[19:8];           //row addr
      else
		ddr_ad_o <= {4'b0101,u_addr[7:0]};    //col addr, 
   end
   always @(negedge clk) begin
      ddr_ad_o_P1 <= ddr_ad_o;	 
      ddr_ba_o_P1 <= ddr_ba_o;
   end
        
   always @(posedge clk) begin
      if (reset2) begin
	 cas_lat_max <= 3'b00;
      end
      else begin 
	 if (mrs_addr) begin
	    cas_lat_max <= next_cas_lat_max;
	    cas_lat_half <= {2{next_cas_lat_half}};
	    burst_2 <= next_burst_2;
	    burst_8 <= next_burst_8;
	 end
      end