readme.txt

DDR（双速率）SDRAM控制器参考设计

***********************ReadMe for XAPP253*********************

Contents of xapp253.zip file

       contains verilog source files
       *top.v* is the source file for DDR SDRAM controller
       *tb_top.v* is the source file for testbench
       *define.v* contains variable definitions
       *mt46v4m16.v* is the simulation model of 64MB DDR SDRAM from Micron

*top.ucf* is the user constraint file to be specified during 
        Place and Route. This contains the constraints for 133MHz implementation