exp17.vhd

vhdl语言实现的频率发生器

                             -------------------------------------
                             --  Title:频率计                   --
		                     --  Author:Zong Zhanhua            --
                             --  Data: 2004-9-16                --
                             -------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------
entity exp17 is
  port( Clk       :  in   std_logic;   --时钟输入
        fin       :  in   std_logic;   --被测频率输入
        Display   :  out  std_logic_vector(7 downto 0);  --七段码管显示输出
        SEG_SEL   :  buffer  std_logic_vector(2 downto 0) --七段码管扫描驱动
       );      
end exp17;
--------------------------------------------------------------------
architecture behave of exp17 is
  signal Disp_Temp     : integer range 0 to 15;
  signal Disp_Decode   : std_logic_vector(7 downto 0);
  signal F1,F2,F3,F4,F5,F6,F7,F8  : integer range 0 to 9;
  signal FF1,FF2,FF3,FF4,FF5,FF6,FF7,FF8  : integer range 0 to 9; 

  signal Clk_Count1    : std_logic_vector(9 downto 0);   --产生0.5Hz时钟的分频计数器
  signal Clk1Hz        : std_logic;
  signal Door_Flag     : std_logic;
  signal Last_Door     : std_logic;
   
  begin
    process(Clk) 
      begin
        if(Clk'event and Clk='1') then
           if(Clk_Count1<1000) then
             Clk_Count1<=Clk_Count1+1;
           else 
             Clk_Count1<="0000000001";
           end if;
        end if;
    end process;
    Clk1Hz<=Clk_Count1(9);
    process(Clk1Hz)
      begin
        if(Clk1Hz'event and Clk1Hz='1') then
           Door_Flag<=not Door_Flag;
        end if;
    end process;

    process(fin)
      begin
        if(fin'event and fin='1') then    --正常运行
           if(Door_Flag='0') then         --数据清零
              F1<=0;
              F2<=0;
              F3<=0;
              F4<=0;
              F5<=0;
              F6<=0;
              F7<=0;
              F8<=0;
           else
              if(F1=9) then
                 F1<=0;
                 if(F2=9) then
                    F2<=0;
                    if(F3=9) then
                       F3<=0;
                       if(F4=9) then
                          F4<=0;
                          if(F5=9) then
                             F5<=0;
                             if(F6=9) then
                                F6<=0;
                                if(F7=9) then
                                  F7<=0;
                                  if(F8=9) then
                                     F8<=0;
                                  else
                                     F8<=F8+1;
                                  end if;
                                else 
                                  F7<=F7+1;
                                end if;
                             else 
                                F6<=F6+1;
                             end if;
                          else
                             F5<=F5+1;
                          end if;
                       else
                          F4<=F4+1;
                       end if;
                    else 
                       F3<=F3+1;
                    end if;
                 else
                    F2<=F2+1;
                 end if;
              else
                 F1<=F1+1;
              end if;
           end if;
        end if; 
    end process;

    process(Door_Flag)
      begin
        if(Door_Flag'event and Door_Flag='0') then
           FF1<=F1;
           FF2<=F2;
           FF3<=F3;
           FF4<=F4;
           FF5<=F5;
           FF6<=F6;
           FF7<=F7;
           FF8<=F8;
        end if;
    end process;

    process(SEG_SEL)      
      begin
        case (SEG_SEL+1) is
          when "000"=>Disp_Temp<=FF8;
          when "001"=>Disp_Temp<=FF7;
          when "010"=>Disp_Temp<=FF6;
          when "011"=>Disp_Temp<=FF5;
          when "100"=>Disp_Temp<=FF4;
          when "101"=>Disp_Temp<=FF3;
          when "110"=>Disp_Temp<=FF2;
          when "111"=>Disp_Temp<=FF1;
       end case;   
    end process;

    process(Clk)
      begin
        if(Clk'event and Clk='1') then    --扫描累加 
           SEG_SEL<=SEG_SEL+1;
           Display<=Disp_Decode;
        end if;
    end process;
    process(Disp_Temp)      --显示转换
      begin
        case Disp_Temp is
          when 0=>Disp_Decode<="00111111";   --0
          when 1=>Disp_Decode<="00000110";   --1
          when 2=>Disp_Decode<="01011011";   --2
          when 3=>Disp_Decode<="01001111";   --3
          when 4=>Disp_Decode<="01100110";   --4
          when 5=>Disp_Decode<="01101101";   --5
          when 6=>Disp_Decode<="01111101";   --6
          when 7=>Disp_Decode<="00000111";   --7
          when 8=>Disp_Decode<="01111111";   --8
          when 9=>Disp_Decode<="01101111";   --9
          when 10=>Disp_Decode<="01000000";   ---
          when others=>Disp_Decode<="00000000";   --全灭
        end case;
    end process;   

end behave;