filter.v

65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程

//////////////////////////////////////////
module  filter (
clk, rst_,
din_i, filter_nd_i,
dout_o, dout_rdy_o
);

// port definitions:
   input clk ; wire clk ;
   input rst_ ; wire rst_ ;
   input [9:0] din_i ; wire [9:0] din_i ;
   input filter_nd_i ; wire filter_nd_i ;
   output [32:0] dout_o ; reg [32:0] dout_o ;
   output dout_rdy_o ; reg dout_rdy_o ;

//constants:
	parameter	SampData_width=15;

	parameter    k0 = 16'b1000000001001110;			//-78
	parameter	k1 = 16'b0000000000001100;			//12
	parameter	k2 = 16'b0000000001100111;			//103
	parameter	k3 = 16'b0000000001110110;			//118
	parameter	k4 = 16'b0000000000100100;			//36
	parameter	k5 = 16'b1000000001010010;			//-82
	parameter	k6 = 16'b1000000010001000;			//-136
	parameter	k7 = 16'b1000000001000111;			//-71
	parameter	k8 = 16'b0000000001000000;			//64
	parameter	k9 = 16'b0000000010010110;			//150
	parameter	k10 = 16'b0000000001011100;		//92
	parameter	k11 = 16'b1000000001010001;		//-81
	parameter	k12 = 16'b1000000011011100;		//-220
	parameter	k13 = 16'b1000000010101001;		//-169
	parameter	k14 = 16'b0000000001011001;		//89
	parameter	k15 = 16'b0000000101110110;		//374
	parameter	k16 = 16'b0000000110100001;		//417
	parameter	k17 = 16'b0000000001001100;		//76
	parameter	k18 = 16'b1000000111101001;		//-489
	parameter	k19 = 16'b1000001101011010;		//-858
	parameter	k20 = 16'b1000001001110010;		//-626
	parameter	k21 = 16'b0000000011110100;		//244
	parameter	k22 = 16'b0000010011110001;		//1265
	parameter	k23 = 16'b0000011001101110;		//1646
	parameter	k24 = 16'b0000001100101011;		//811
	parameter	k25 = 16'b1000010000101101;		//-1069
	parameter	k26 = 16'b1000101101111001;		//-2937
	parameter	k27 = 16'b1000110011001001;		//-3273
	parameter	k28 = 16'b1000001110101011;		//-939
	parameter	k29 = 16'b0000111111001000;		//4040
	parameter	k30 = 16'b0010100000000010;		//10242
	parameter	k31 = 16'b0011110000010010;		//15378
	parameter	k32 = 16'b0100001111011001;		//17369
	parameter	k33 = 16'b0011110000010010;		//15378
	parameter	k34 = 16'b0010100000000010;		//10242
	parameter	k35 = 16'b0000111111001000;		//4040
	parameter	k36 = 16'b1000001110101011;		//-939
	parameter	k37 = 16'b1000110011001001;		//-3273
	parameter	k38 = 16'b1000101101111001;		//-2937
	parameter	k39 = 16'b1000010000101101;		//-1069
	parameter	k40 = 16'b0000001100101011;		//811
	parameter	k41 = 16'b0000011001101110;		//1646
	parameter	k42 = 16'b0000010011110001;		//1265
	parameter	k43 = 16'b0000000011110100;		//244
	parameter	k44 = 16'b1000001001110010;		//-626
	parameter	k45 = 16'b1000001101011010;		//-858
	parameter	k46 = 16'b1000000111101001;		//-489
	parameter	k47 = 16'b0000000001001100;		//76
	parameter	k48 = 16'b0000000110100001;		//417
	parameter	k49 = 16'b0000000101110110;		//374
	parameter	k50 = 16'b0000000001011001;		//89
	parameter	k51 = 16'b1000000010101001;		//-169
	parameter	k52 = 16'b1000000011011100;		//-220
	parameter	k53 = 16'b1000000001010001;		//-81
	parameter	k54 = 16'b0000000001011100;		//92
	parameter	k55 = 16'b0000000010010110;		//150
	parameter	k56 = 16'b0000000001000000;		//64
	parameter	k57 = 16'b1000000001000111;		//-71
	parameter	k58 = 16'b1000000010001000;		//-136
	parameter	k59 = 16'b1000000001010010;		//-82
	parameter	k60 = 16'b0000000000100100;		//36
	parameter	k61 = 16'b0000000001110110;		//118
	parameter	k62 = 16'b0000000001100111;		//103
	parameter	k63 = 16'b0000000000001100;		//12
	parameter	k64 = 16'b1000000001001110;		//-78

// signals:
	reg	[7:0]	temp_rep;
	reg	[650:0]	reg_data_sft;
	reg	[4:0] counter_out;
	reg	shift_on;
	reg	sumtaps_on;
	reg	accum_on;

	reg	[21:0]	sumtaps_plus;
	reg	[21:0]	sumtaps_neg;
	reg	[30:0]	sft_plus_reg;
	reg	[30:0]	sft_neg_reg;
	reg	[31:0]	accum_plus;
	reg	[31:0]	accum_neg;
//	reg	delay_data_ready_o;

	//tap coefficient registers:
	reg	[SampData_width-1 : 0]	f0;
	reg	[SampData_width-1 : 0]	f1;
	reg	[SampData_width-1 : 0]	f2;
	reg	[SampData_width-1 : 0]	f3;
	reg	[SampData_width-1 : 0]	f4;
	reg	[SampData_width-1 : 0]	f5;
	reg	[SampData_width-1 : 0]	f6;
	reg	[SampData_width-1 : 0]	f7;
	reg	[SampData_width-1 : 0]	f8;
	reg	[SampData_width-1 : 0]	f9;
	reg	[SampData_width-1 : 0]	f10;
	reg	[SampData_width-1 : 0]	f11;
	reg	[SampData_width-1 : 0]	f12;
	reg	[SampData_width-1 : 0]	f13;
	reg	[SampData_width-1 : 0]	f14;
	reg	[SampData_width-1 : 0]	f15;
	reg	[SampData_width-1 : 0]	f16;
	reg	[SampData_width-1 : 0]	f17;
	reg	[SampData_width-1 : 0]	f18;
	reg	[SampData_width-1 : 0]	f19;
	reg	[SampData_width-1 : 0]	f20;
	reg	[SampData_width-1 : 0]	f21;
	reg	[SampData_width-1 : 0]	f22;
	reg	[SampData_width-1 : 0]	f23;
	reg	[SampData_width-1 : 0]	f24;
	reg	[SampData_width-1 : 0]	f25;
	reg	[SampData_width-1 : 0]	f26;
	reg	[SampData_width-1 : 0]	f27;
	reg	[SampData_width-1 : 0]	f28;
	reg	[SampData_width-1 : 0]	f29;
	reg	[SampData_width-1 : 0]	f30;
	reg	[SampData_width-1 : 0]	f31;
	reg	[SampData_width-1 : 0]	f32;
	reg	[SampData_width-1 : 0]	f33;
	reg	[SampData_width-1 : 0]	f34;
	reg	[SampData_width-1 : 0]	f35;
	reg	[SampData_width-1 : 0]	f36;
	reg	[SampData_width-1 : 0]	f37;
	reg	[SampData_width-1 : 0]	f38;
	reg	[SampData_width-1 : 0]	f39;
	reg	[SampData_width-1 : 0]	f40;
	reg	[SampData_width-1 : 0]	f41;
	reg	[SampData_width-1 : 0]	f42;
	reg	[SampData_width-1 : 0]	f43;
	reg	[SampData_width-1 : 0]	f44;
	reg	[SampData_width-1 : 0]	f45;
	reg	[SampData_width-1 : 0]	f46;
	reg	[SampData_width-1 : 0]	f47;
	reg	[SampData_width-1 : 0]	f48;
	reg	[SampData_width-1 : 0]	f49;
	reg	[SampData_width-1 : 0]	f50;
	reg	[SampData_width-1 : 0]	f51;
	reg	[SampData_width-1 : 0]	f52;
	reg	[SampData_width-1 : 0]	f53;
	reg	[SampData_width-1 : 0]	f54;
	reg	[SampData_width-1 : 0]	f55;
	reg	[SampData_width-1 : 0]	f56;
	reg	[SampData_width-1 : 0]	f57;
	reg	[SampData_width-1 : 0]	f58;
	reg	[SampData_width-1 : 0]	f59;
	reg	[SampData_width-1 : 0]	f60;
	reg	[SampData_width-1 : 0]	f61;
	reg	[SampData_width-1 : 0]	f62;
	reg	[SampData_width-1 : 0]	f63;	
	reg	[SampData_width-1 : 0]	f64; 

    reg [21 : 0]    SumTaps_neg_1_1;
    reg [21 : 0]    SumTaps_neg_1_2;
    reg [21 : 0]    SumTaps_neg_1_3;
    reg [21 : 0]    SumTaps_neg_1_4;
    reg [21 : 0]    SumTaps_neg_1_5;
    reg [21 : 0]    SumTaps_neg_1_6;
    reg [21 : 0]    SumTaps_neg_1_7;
    reg [21 : 0]    SumTaps_neg_2_1;
    reg [21 : 0]    SumTaps_neg_2_2;
//    reg [21 : 0]    SumTaps_neg_2_3;
//    reg [21 : 0]    SumTaps_neg_2_4;

    reg [21 : 0]    SumTaps_plus_1_1;
    reg [21 : 0]    SumTaps_plus_1_2;
    reg [21 : 0]    SumTaps_plus_1_3;
    reg [21 : 0]    SumTaps_plus_1_4;
    reg [21 : 0]    SumTaps_plus_1_5;
    reg [21 : 0]    SumTaps_plus_1_6;
    reg [21 : 0]    SumTaps_plus_1_7;
    reg [21 : 0]    SumTaps_plus_1_8;
    reg [21 : 0]    SumTaps_plus_1_9;
    reg [21 : 0]    SumTaps_plus_1_10;
    reg [21 : 0]    SumTaps_plus_2_1;
    reg [21 : 0]    SumTaps_plus_2_2;
    reg [21 : 0]    SumTaps_plus_2_3;
//    reg [21 : 0]    SumTaps_plus_2_3;
//    reg [21 : 0]    SumTaps_plus_2_4;


// code:
//////////////////////////////////////////////////////////////////
/////counter process//////////////////////////////////////////////
	always @(posedge clk or negedge rst_)		// counter
	begin
		if(!rst_)
		begin
			temp_rep <= 8'b0;
			counter_out <= 5'b11111;
			shift_on <= 1'b0;
			sumtaps_on <= 1'b0;
			accum_on <= 1'b0;
			dout_rdy_o <= 1'b0;
		end
		else
		begin
			if(filter_nd_i)
				counter_out <= 5'b0;                
			else if(counter_out != 5'b11111)
				counter_out <= counter_out + 1'b1;
			if(counter_out==5'b00101)
				accum_on <= 1'b1;
			if(counter_out==5'b10000)
			begin
				accum_on <= 1'b0;
				dout_rdy_o <= 1'b1;
			end
			else
				dout_rdy_o <= 1'b0;
			if(counter_out==5'b0)
				shift_on <= 1'b1;
			if(counter_out==5'b00001)
				sumtaps_on <= 1'b1;
			if(counter_out==5'b01010)
				shift_on <= 1'b0;
			if(counter_out==5'b01110)
				sumtaps_on <= 1'b0;
		end
	end

///////////////////////////////////////////////////////////////////
/////taps process//////////////////////////////////////////////////
	always @(posedge clk or negedge rst_)		//taps shift register
	begin
		if(!rst_)
		begin
			reg_data_sft <= {{65{10'b1000000000}},1'b1};
		end
		else if(filter_nd_i)
			for(temp_rep=0;temp_rep<10;temp_rep=temp_rep+1'b1)
          	begin 
          		if (temp_rep==0)  
             			reg_data_sft[temp_rep] <=~din_i[9-temp_rep];
          		else
			      	reg_data_sft[temp_rep] <= din_i[9-temp_rep];
          	end
			else if(shift_on)
				reg_data_sft <= reg_data_sft<<1;
	end

///////////////////////////////////////////////////////////////////////
////////sum taps process///////////////////////////////////////////////
	always @(posedge clk or negedge rst_)		//sumtaps
	begin
		if(!rst_)
		begin
			//initialize signals
			sumtaps_neg <= 22'b0;
			sumtaps_plus <= 22'b0;
	       	SumTaps_plus_1_1<=22'b0;
       		SumTaps_plus_1_2<=22'b0;
       		SumTaps_plus_1_3<=22'b0;
       		SumTaps_plus_1_4<=22'b0;
       		SumTaps_plus_1_5<=22'b0;
       		SumTaps_plus_1_6<=22'b0;
       		SumTaps_plus_1_7<=22'b0;
       		SumTaps_plus_1_8<=22'b0; 
       		SumTaps_plus_1_9<=22'b0;   
       		SumTaps_plus_1_10<=22'b0;   
       		SumTaps_plus_2_1<=22'b0;
       		SumTaps_plus_2_2<=22'b0;
       		SumTaps_plus_2_3<=22'b0;