chapter10_models.vhd

James Armstrong VHDL Design , source code

     C_UNSIGNED  := CONV_UNSIGNED(A_UNSIGNED,5) + 
      UNSIGNED(B) +  UNSIGNED(PADDED_CIN);
     C  <= STD_LOGIC_VECTOR(C_UNSIGNED(3 downto 0));      CAR_OUT  <= 
C_UNSIGNED(4);
   end process;
end ALG;
---Figure 10.36 Adder Model

library IEEE,DW02;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use DW02.DW02_components.all;

entity MULT10 is
port(DATA_IN: in STD_LOGIC_VECTOR(3 downto 0); 
     PRODUCT: out STD_LOGIC_VECTOR(7 downto 0));
end MULT10;

architecture ALG of MULT10 is
  begin
  process(DATA_IN)
    variable PROD_US: UNSIGNED(7 downto 0);
  begin
    PROD_US := UNSIGNED(DATA_IN)*CONV_UNSIGNED(10,4);
    PRODUCT <= STD_LOGIC_VECTOR(PROD_US);
  end process;
end ALG;
--Figure 10.37 Multiply By 10 Model
library IEEE,DW02;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use DW02.DW02_components.all;

entity MADD is
generic(IN_WIDTH: NATURAL := 4);
port(DI: in STD_LOGIC_VECTOR(IN_WIDTH-1 downto 0); 
     DJ: in STD_LOGIC_VECTOR(3 downto 0);
     MSUM: out STD_LOGIC_VECTOR(IN_WIDTH+3 downto 0));
end MADD;

architecture ALG of MADD is
  begin
  P1: process(DI,DJ)
    variable MSUM_US: UNSIGNED(IN_WIDTH+3 downto 0);
     variable PROD:UNSIGNED(2*IN_WIDTH-1 downto 0);
 
  begin
    PROD :=  UNSIGNED(DI)*CONV_UNSIGNED(10,IN_WIDTH);
    MSUM_US := PROD(IN_WIDTH+3 downto 0)+ UNSIGNED(DJ);
    MSUM <= STD_LOGIC_VECTOR(MSUM_US);
  end process;
end ALG;
--Figure 10.40 Multiply By 10 and Add Model

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BCDCONV is
port(D0,D1,D2,D3: in STD_LOGIC_VECTOR(3 downto 0);
      BIN_OUT: out STD_LOGIC_VECTOR(15 downto 0));
end BCDCONV;

architecture STRUCTURAL of BCDCONV is

component MADD 
generic(IN_WIDTH: NATURAL := 4);
port(DI: in STD_LOGIC_VECTOR(IN_WIDTH-1 downto 0); 
     DJ: in STD_LOGIC_VECTOR(3 downto 0);
     MSUM: out STD_LOGIC_VECTOR(IN_WIDTH+3 downto 0));
end component;
signal MSUM2: STD_LOGIC_VECTOR(7 downto 0);
signal MSUM1:  STD_LOGIC_VECTOR(11 downto 0);
begin
C1: MADD
  generic map(4)
  port map(D3,D2,MSUM2);
C2: MADD
  generic map(8)
  port map(MSUM2,D1,MSUM1);
C3: MADD
  generic map(12)
  port map(MSUM1,D0,BIN_OUT);
end STRUCTURAL;
--Figure 10.41 Structural Model of the BCD to Binary Converter

entity ADD_12_REG is
port(X,Y: in STD_LOGIC_VECTOR(11 downto 0); CI, CLK: in STD_LOGIC;
      Z:out STD_LOGIC_VECTOR(11 downto 0);CO: out STD_LOGIC);
end ADD_12_REG;
architecture STRUCTURAL of ADD_12_REG is
component SIMP_ADD 
port(A,B: in STD_LOGIC_VECTOR(3 downto 0); CIN: in STD_LOGIC;
      C:out STD_LOGIC_VECTOR(3 downto 0);CAR_OUT: out STD_LOGIC);
end component;
component REG_12
port(DATA_IN: in STD_LOGIC_VECTOR(11 downto 0);CLK: in STD_LOGIC; 
DATA_OUT: out STD_LOGIC_VECTOR(11 downto 0));
end component;
component REG
port(DATA_IN: in STD_LOGIC;CLK: in STD_LOGIC; DATA_OUT: out 
STD_LOGIC);
end component;
signal LO_CAR,MID_CAR,HI_CAR:STD_LOGIC;
signal Z_COMB: STD_LOGIC_VECTOR(11 downto 0);
begin
  C1: SIMP_ADD
   port map(X(3 downto 0),Y(3 downto 0),CI,Z_COMB(3 downto   0), 
LO_CAR);
  C2: SIMP_ADD
   port map(X(7 downto 4),Y(7 downto 4),LO_CAR,Z_COMB(7 downto 4), 
MID_CAR);
  C3: SIMP_ADD
   port map(X(11 downto 8),Y(11 downto 8),LO_CAR,Z_COMB(11 downto 8), 
HI_CAR);
  C4: REG_12
   port map(Z_COMB,CLK,Z);
  C5: REG
   port map(HI_CAR,CLK,CO);
end STRUCTURAL;
--Figure 1.46 12 Bit Adder Model

entity INFERRED is
port(IN_DAT,IN_EN: in STD_LOGIC; SEL: in STD_LOGIC_VECTOR(1 downto 0); 
    A_LATCHED,A_COMB,B_LATCHED,B_COMB_0,B_COMB_1,B_COMB_2: out 
STD_LOGIC);
--pragma dc_script_begin
--set_flatten true
--pragma dc_script_end

end INFERRED;

architecture ALG of INFERRED is
begin

P_A_LATCHED: process(IN_DAT,IN_EN)
 begin
  if IN_EN = '1' then
    A_LATCHED <= IN_DAT;
  end if;
end process;
P_A_COMB: process(IN_DAT,IN_EN)
 begin
  if IN_EN = '1' then
    A_COMB <= IN_DAT;
  else
    A_COMB <= '0'; 
  end if;
end process;
P_B_LATCHED: process(IN_DAT,SEL)
begin
  case (SEL) is
    when "00" => B_LATCHED <= IN_DAT;
    when "01" => B_LATCHED <= not IN_DAT;
    when  "10" => B_LATCHED <= '0';
    when  "11" =>  null;
    when others => null;
  end case;
end process;
P_B_COMB_0: process(IN_DAT,SEL)
begin
  case (SEL) is
    when "00" => B_COMB_0 <= IN_DAT;
    when "01" => B_COMB_0 <= not IN_DAT;
    when  "10" => B_COMB_0 <= '0';
    when  "11" => B_COMB_0 <= '1';
    when others => null;
  end case; 
end process; 
  P_B_COMB_1: process(IN_DAT,SEL)
  begin
  B_COMB_1 <= '1';
  case (SEL) is
    when "00" => B_COMB_1 <= IN_DAT;
    when "01" => B_COMB_1 <= not IN_DAT;
    when  "10" => B_COMB_1 <= '0';
    when  "11" => null;
    when others => null;
  end case;
end process;
P_B_COMB_2: process(IN_DAT,SEL)
  begin
   case (SEL) is
    when "00" => B_COMB_2 <= IN_DAT;
    when "01" => B_COMB_2 <= not IN_DAT;
    when "10" => B_COMB_2 <= '0';
    when "11" => B_COMB_2 <= '-';
    when others => null;
  end case;
 end process;
end ALG;  
--Figure 10.51 Inferred Latches and Don't Cares Model

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FUNCS is
port(X: in STD_LOGIC_VECTOR(2 downto 0); Z1,Z2: out STD_LOGIC);
--pragma dc_script_begin
--set_flatten true
--pragma dc_script_end
end FUNCS;

architecture ROM of FUNCS is
type ROM_1D is array(0 to 7) of STD_LOGIC;
begin
FULLY_SPECIFIED: process(X)
  constant ROM1: ROM_1D:= "01101000";
  begin
    Z1 <=ROM1(CONV_INTEGER(X));
end process; 
PARTIALLY_SPECIFIED: process(X)
  constant ROM2: ROM_1D:= "01101--0";
  begin
    Z2 <=ROM2(CONV_INTEGER(X));
end process;
end ROM;
--Figure 10.53 Two ROM Model

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TRISTATE is
port(A,B,ENA,ENB: in STD_LOGIC; BUS_SIG: out STD_LOGIC);
end TRISTATE;

architecture   ALG of  TRISTATE is
  begin
PROCA: process(A,ENA)
  begin
  if (ENA = '1') then
     BUS_SIG <= A;
  else 
     BUS_SIG <= 'Z';
  end if;
end process;
PROCB: process(B,ENB)
  begin
  if (ENB = '1') then
     BUS_SIG <= B;
  else 
     BUS_SIG <= 'Z';
  end if;
end process;
end   ALG;
--Figure 10.55 Tristate Circuit  Model

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity SHARE_1 is
  port(A,B,C,D: in STD_LOGIC_VECTOR(3 downto 0); SEL_CD: in STD_LOGIC;
       F: out STD_LOGIC_VECTOR(3 downto 0));
end SHARE_1;
architecture DF of SHARE_1 is
  signal MUX1,MUX2:SIGNED(3 downto 0);
  signal SUM:SIGNED(3 downto 0);  
  begin
      MUX1 <= SIGNED(A)when SEL_CD = '0' else SIGNED(C);
      MUX2 <= SIGNED(B) when SEL_CD = '0' else SIGNED(D);
      SUM <= MUX1 + MUX2;
      F <= STD_LOGIC_VECTOR(SUM);
end DF;
--Figure 10.57 Multiplex Then Add Model

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity SHARE_2 is
  port(A,B,C,D: in STD_LOGIC_VECTOR(3 downto 0); SEL_CD: in STD_LOGIC;        
F: out STD_LOGIC_VECTOR(3 downto 0));
end SHARE_2;
architecture DF of SHARE_2 is
  signal ADD1,ADD2:SIGNED(3 downto 0);  
  begin
      ADD1 <= SIGNED(A) + SIGNED(B);
      ADD2 <= SIGNED(C) + SIGNED(D);
      F <= STD_LOGIC_VECTOR(ADD1) when SEL_CD = '0'
           else STD_LOGIC_VECTOR(ADD2);
 end DF;
--Figure 10.58 Add Then Multiplex Model

entity LOG_FUNC is
port(A,B,C,D: in STD_LOGIC; F: out STD_LOGIC);
--pragma dc_script_begin
--set_flatten true
--pragma dc_script_end
end LOG_FUNC;

architecture DF of LOG_FUNC is
  signal S1,S2: STD_LOGIC;
    begin
     S1 <= A or B;
     S2 <= S1 and C;
     F <= S2 and D;
end DF;
--Figure 10.61 Three Level Circuit
entity LOG_FUNC is
port(A,B,C,D: in STD_LOGIC; F1,F2: out STD_LOGIC);
--pragma dc_script_begin
--set_structure -timing true
--pragma dc_script_end
end LOG_FUNC;

architecture DF of LOG_FUNC is
    begin
     F1 <= (A and B) or (A and D);
     F2 <= (B and C) or (C and D);
end DF; 
--Figure 10.63 Two Level Model

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX is
 port (SEL: in STD_LOGIC_VECTOR(1 downto 0);
       A,B,C,D: in STD_LOGIC;
       MUX_OUT: out STD_LOGIC);
end MUX;
architecture IF_STATEMENT of MUX is
 begin
  process(SEL,A,B,C,D)
  begin
  if (SEL = "00") then MUX_OUT <= A;
  elsif (SEL = "01") then MUX_OUT <= B;
  elsif (SEL = "10") then MUX_OUT <= C;
  elsif (SEL = "11") then MUX_OUT <= D;
  else  MUX_OUT <= '0';
  end if;
  end process;
end IF_STATEMENT;

architecture CASE_STATEMENT of MUX is
 begin
  process(SEL,A,B,C,D)
  begin
  case SEL is
  when "00" => MUX_OUT <= A;
  when "01" => MUX_OUT <= B;
  when "10" => MUX_OUT <= C;
  when "11" => MUX_OUT <= D;
  when others => MUX_OUT <= '0';
  end case;
  end process;
end CASE_STATEMENT;  
--Figure 10.65 If and Case Implementation of a Muliplexer.