chapter10_models.vhd

James Armstrong VHDL Design , source code

entity DECIMATE is
generic (DEC: INTEGER);
    port ( RX,IX: in REAL:=0.0;
	   N:  in REAL:=0.0;
	   RY,IY: out REAL:=0.0;);
end DECIMATE;
architecture BEHAVIOR of DECIMATE is
    begin
	process
	    variable cnt: integer :=0;
	begin
	    wait on N;
	    cnt := integer(N) rem DEC;
	    if cnt = 0 then
		RY <= RX;
		IY <= IX;
	    end if;
	end process;
end BEHAVIOR;
--Figure 10. 12 High-Level Decimation Block

library IEEE;
use IEEE.std_logic_1164.all;
entity PAR_TO_SER is
port(START,SHCLK: in STD_LOGIC; PAR_IN: in STD_LOGIC_VECTOR(7 downto 
0);
      SO: out STD_LOGIC);
end PAR_TO_SER;

architecture ALG1 of PAR_TO_SER is
 begin
P1:process(START,SHCLK)
   variable COUNT: INTEGER range 7 downto -1 := 0;
   variable DONE: BOOLEAN;
begin
   if  START = '1' then 
     COUNT := 7;
     DONE := FALSE;
   elsif SHCLK'EVENT and SHCLK = '1'  then 
     if DONE = FALSE then 
      SO <= PAR_IN(COUNT);
      COUNT := COUNT - 1;
     end if; 
     if COUNT < 0 then
      DONE := TRUE;
     else
      DONE  := FALSE;
     end if;
   end if;
end process;
end ALG1;
---Figure 10.13 Clocked Parallel to Serial Converter

use IEEE.std_logic_1164.all;
entity PAR_TO_SER_SCHED is
generic(PERIOD: TIME);
port(START: in STD_LOGIC; PAR_IN: in STD_LOGIC_VECTOR(7 downto 0);
      SO: out STD_LOGIC);
end PAR_TO_SER_SCHED;
architecture ALG2 of PAR_TO_SER_SCHED is
begin
P1:process(START)
   variable COUNT: INTEGER;
begin
   if  START = '1' then 
     COUNT := 7;
     while COUNT >= 0 loop
     SO <= transport PAR_IN(COUNT) after (7-COUNT)*PERIOD;
     COUNT := COUNT - 1;
     end loop;
    end if;
end process;
end ALG2;
--Figure 10.15 Scheduled Parallel to Serial Converter

entity T_FF is
port(RESET,T,CLK: in STD_LOGIC; QOUT: out STD_LOGIC);
end T_FF; 
architecture ALG of T_FF is
signal Q: STD_LOGIC;
begin
process(RESET,T,CLK)
 begin
   if (RESET = '1') then
      Q  <= '0';
   elsif (CLK'EVENT and CLK = '1') then 
      if T = '1' then
      Q  <=  not Q ;
      end if; 
   end if;
end process;
     QOUT <= Q;
end ALG;
--Figure 10. 18 TFF Flip-flop Model That Simulates Correctly

entity T_FF2 is
port(RESET,T,CLK: in STD_LOGIC; QOUT: out STD_LOGIC);
end T_FF2; 
architecture ALG of T_FF2 is
signal Q: STD_LOGIC;
begin
process(RESET,T,CLK)
 begin
   if (RESET = '1') then
      Q  <= '0';
   elsif (CLK'EVENT and CLK = '1') then 
      if T = '1' then
      Q  <=  not Q ;
      end if; 
   end if;
   QOUT <= Q;
end process;
end ALG;
--Figure 10.19 T Flip-flop Model That Simulates Incorrectly

entity EQDET is
port(I,CLK: in STD_LOGIC;  TEQDET: inout STD_LOGIC :='0'); 
end EQDET;

architecture ALG of EQDET is
  begin
  process
    variable  EQ,IBK1,IBK2: STD_LOGIC;
    begin
    wait until (CLK'EVENT and CLK = '1');
      if(IBK1 =IBK2) and (IBK2 = I) then 
        EQ := '1';
       else
        EQ := '0';
      end if;
      TEQDET <= (EQ xor TEQDET);
      IBK2 := IBK1;
      IBK1 := I;
  end process;
end ALG;
--Figure 10.22 Initial Equality Detector Model

entity EQDET is
port(RESET,I,CLK: in STD_LOGIC;  TEQDET: inout STD_LOGIC);
end EQDET;

architecture ALG of EQDET is
  begin
  process(RESET,CLK)
    variable  EQ,IBK1,IBK2: STD_LOGIC;
    begin
       if (RESET = '1') then
        IBK1 :=  '0';
        IBK2 :=  '0';
          TEQDET <= '0';
       elsif (CLK'EVENT and CLK = '1') then
        if (IBK1 = I) and (IBK1 = IBK2) then 
         EQ := '1';
        else
         EQ := '0';
        end if;
        TEQDET <= (EQ xor TEQDET);
         IBK2 := IBK1;
        IBK1 := I;
       end if;
  end process;
end ALG;
--Figure 10.23 Equality Detector with Reset in If-Then Structure

entity EQDET is
port(RESET,I,CLK: in STD_LOGIC;  TEQDET: inout STD_LOGIC);
end EQDET;

architecture ALG of EQDET is
  signal IBK1,IBK2: STD_LOGIC;
  begin
  process(RESET,CLK)
    variable  EQ: STD_LOGIC;
    begin
       if (RESET = '1') then
        IBK1 <=  '0';
        IBK2  <=  '0';
          TEQDET <= '0';
       elsif (CLK'EVENT and CLK = '1') then
        if (IBK1 = I) and (IBK1 = IBK2) then 
         EQ := '1';
        else
         EQ := '0';
        end if;
        TEQDET <= (EQ xor TEQDET);
        IBK1 <= I;
        IBK2  <= IBK1;
       end if;
  end process;
end ALG;
--Figure 10.26 Signal Based Model

entity EQDET is
port(RESET,I,CLK: in  STD_LOGIC; TEQDET: inout STD_LOGIC);
end EQDET;
architecture FSM of EQDET is
 begin
P1:process(RESET,CLK)
type STATE_TYPE is (S0,S1,S2);
variable STATE: STATE_TYPE;
variable IBK1: STD_LOGIC;
begin
 if RESET = '1' then
   STATE := S0;
   IBK1 := '0';
   TEQDET <= '0';
 elsif (CLK'EVENT and CLK = '1') then
  case (STATE) is
  when S0 =>
   STATE := S1; 
   IBK1 := I;
  when S1 =>
   if (IBK1 = I) then
   STATE := S2;
   else
   STATE := S1;
   end if;
   IBK1 := I;
  when S2 =>
   if (IBK1 = I) then
   STATE := S2;
   TEQDET <= not TEQDET;
    else
   STATE := S1;
   end if;
  IBK1 := I;
  end case;
end if;
end process;
end FSM;
--Figure 10.28  Detector FSM Model

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use  IEEE.std_logic_arith.all;  

entity ONES_CNT  is
port (A: in STD_LOGIC_VECTOR(2 downto 0); C: out STD_LOGIC_VECTOR(1 
downto 0));
end ONES_CNT;
(a)

architecture DATA_FLOW of ONES_CNT  is
begin
 C(1) <= (A(1) and A(0)) or (A(2) and A(0))
          or (A(2) and A(1));
 C(0) <= (A(2) and not A(1) and not A(0))
          or (not A(2) and not A(1) and A(0))
          or (A(2) and A(1) and A(0))
          or (not A(2) and A(1) and not A(0));
end DATA_FLOW;
			(b)

architecture MUX of ONES_CNT is
begin

 process(A)
 begin 
  case A is
   when "000" => C<= "00";
   when "001"|"010"|"100" => C<= "01";
   when "011"|"101"|"110" => C<= "10";
   when "111" => C<= "11";
   when others => null;
  end case;
 end process;
end MUX;
		      (c)

architecture ROM of ONES_CNT is
begin
 process (A)
     type ROM_TABLE is array( 0 to 7)
      of STD_LOGIC_VECTOR(1 downto 0);
     constant ROM: ROM_TABLE := 
(('0','0'),('0','1'),('0','1'),('1','0'),
 ('0','1'),('1','0'),('1','0'),('1','1'));
     begin
      C <= ROM(CONV_INTEGER(A));
 end process;
 end ROM;
(d)


architecture ALGORITHMIC of ONES_CNT  is
begin
 P1:process(A)
 variable NUM: INTEGER range 0 to 3; 
 begin
   NUM := 0;  
  for I in 0 to 2 loop
   if A(I) = '1'  then
    NUM := NUM + 1;
   end if;
  end loop;
  case NUM is
   when  0 => C <= "00";
   when  1 => C <= "01";
   when  2 => C <= "10";
   when  3 => C <= "11";
  end case;
end process P1;
end ALGORITHMIC;

 			(e)


architecture PROC of ONES_CNT is
   procedure ONES_CNT_PROC(X : in STD_LOGIC_VECTOR;  Z_SIZE:INTEGER; 
signal Z : out STD_LOGIC_VECTOR) is 
   variable  RES:  STD_LOGIC_VECTOR(Z_SIZE-1 downto 0);
        begin
           RES := CONV_STD_LOGIC_VECTOR(0,Z_SIZE);
           for I in  X'RANGE loop
               if (X(I) = '1') then
                  RES := unsigned(RES) + 1;
                end if;
          end loop;
          Z <= RES;
    end ONES_CNT_PROC;
    begin
        ONES_CNT_PROC(A,2,C);
 end PROC;        
(f)
--Figure 10.31 Ones Count  Architectures

Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity SIMP_ADD is
port(A,B: in STD_LOGIC_VECTOR(3 downto 0);
     CIN: in STD_LOGIC;
     C: out STD_LOGIC_VECTOR(3 downto 0);CAR_OUT: out STD_LOGIC);
end SIMP_ADD;
architecture ALG of SIMP_ADD is
  begin
  P1:process(A,B,CIN)
    variable  PADDED_CIN: STD_LOGIC_VECTOR(3 downto 0);
    variable A_UNSIGNED: UNSIGNED(3 downto 0);
    variable C_UNSIGNED: UNSIGNED(4 downto 0);
  begin
     A_UNSIGNED := UNSIGNED(A);
     PADDED_CIN  :="000"&CIN;