chapter11_models.vhd

James Armstrong VHDL Design , source code

         MAG_OUT: inout PIXEL:= 0; -- edge pixel value
         DIR: inout DIRECTION :="000"); -- edge direction
  end component;
-- intermediate signals between the components --
  signal E_H,E_V,E_DL,E_DR: FILTER_OUT:=0;
  signal MEM_OUT1, MEM_OUT2, MEM_OUT3: PIXEL:=0;

begin
    ---------- component instantiation -------
MEMP1: MEMORY_PROCESSOR1 
  generic map(NUM_ROWS => NUM_ROWS, NUM_COLS => NUM_COLS
              MEM_OUT_DELAY => 2 ns)
  port map(CLOCK, EDGE_START, INPUT, MEM_OUT1,
           MEM_OUT2, MEM_OUT3);

WINP: WINDOW_PROCESSOR1 
  generic map(HORIZ_DELAY => 3 ns, VERT_DELAY=> 3 ns,
              LEFT_DIAG_DELAY => 3 ns,
              RIGHT_DIAG_DELAY => 3 ns,
              WAIT_TIME => 0 ns)
  port map(CLOCK, MEM_OUT1, MEM_OUT2, MEM_OUT3,
           E_H, E_V, E_DL, E_DR);

MAGP: MAG_PROCESSOR1 
  generic map( MAG_DELAY => 3 ns)
  port map(CLOCK, E_H, E_V, E_DL, E_DR,THRESHOLD,
           OUTPUT, DIR) 
end STRUCTURE; 

-- Figure 11.38
library STRUCT_INT;
use STRUCT_INT.all;

configuration CONFIG_SOBEL_S_L1 of EDGE_DETECTOR is
  for STRUCTURE

    for MEMP1: MEMORY_PROCESSOR1
      use entity STRUC_INT.MEMORY_PROCESSOR(BEHAVIOR);
    end for;

    for WINP: WINDOW_PROCESSOR1
      use entity STRUC_INT.WINDOW_PROCESS(BEHAVIOR);
    end for;

    for MAGP: MAG_PROCESSOR1
      use entity STRUC_INT.MAG_PROCESS(BEHAVIOR);
    end for;
  end for;
end;

-- Figure 11.39
configuration CONFIG_S_INT of TB_CONFIG is
  for TEST_BENCH
    for con:TEST1 use entity BEH_INT.TEST(BENCH) 
      generic map("tesv_i2.dat", "test_o2.dat",
                  "test_d2.dat", 10,10,5);
      for BENCH
        for P1:CLOCK_GENERATOR1 use entity 
          BEH_INT.CLOCK_GENERATOR(BEHAVIOR)
          generic map(HI_TIME=>75 ns,LO_TIME=>25 ns);
        end for;
        for P2:COMP_MAG1
          use entity BEH_INT.COMP_MAG(COMPARE)
          generic map("test_o2.dat","test_gm.dat",10,10);
        end for;
        for P3:COMP_DIR1
          use entity BEH_INT.COMP_DIR(COMPARE)
          generic map("test_d2.dat","test_gd.dat",10,10);
        end for;
        for P4:EDGE_DETECTOR1
          use entity STRUC_INT.CONFIG_SOBEL_S_L1
          generic map(NUM_ROWS=>10,NUM_COLS=>10);
        end for;
      end for;
    end for;
  end for;
end;

-- Figure 11.41
entity TB is
end TB;
architecture HORIZ_TB_INT of TB is
  signal RUN: STD_LOGIC;
  signal CLOCK:STD_LOGIC:='0';
  signal P1,P3: PIXEL:=0;
  signal H: FILTER_OUT:=0;
  component CLOCK_GENERATOR1
    generic(HI_TIME,LO_TIME:TIME);
    port(RUN: in STD_LOGIC;
         CLOCK: out STD_LOGIC);
  end component;
  component  HORIZONTAL_FILTER1 
    generic(HORIZ_DELAY: TIME;
            WAIT_TIME:TIME);
    port(CLOCK: in STD_LOGIC:='0';
         P1,P3: in  PIXEL:=0;
         H: inout FILTER_OUT:=0);
  end component;
  for L1: CLOCK_GENERATOR1
    use entity BEH_INT.CLOCK_GENERATOR(BEHAVIOR);
  for L2: HORIZONTAL_FILTER1
    use entity STRUC_INT.HORIZONTAL_FILTER(BEHAVIOR);
begin
  L1: CLOCK_GENERATOR1
    generic map(HI_TIME=>75 ns,LO_TIME=>25 ns)
    port map(RUN,CLOCK);
  L2: HORIZONTAL_FILTER1
    generic map(HORIZ_DELAY=>1 ns,WAIT_TIME=>100 ns)
    port map(CLOCK,P1,P3,H);
  RUN<='0' after 0 ns,'1' after 5 ns,'0' after 1000 ns;
  P1<=11 after 10 ns,10 after 110 ns,9 after 210 ns,
      12 after 310 ns,13 after 410 ns,48 after 510 ns;
  P3<=8 after 10 ns,40 after 110 ns,7 after 210 ns,
      10 after 310 ns,5 after 410 ns,110 after 510 ns;
end HORIZ_TB_INT;

-- Figure 11.42
-------------ENTITY TEST BENCH---------------
entity TB is
end TB;
-------------ARCHITECTURE BODY---------------
architecture WINDOW_TB of TB is
  signal P1,P2,P3: PIXEL:=0;
  signal CLOCK:  STD_LOGIC:='0';
  signal W_H: FILTER_OUT:=0;
  signal W_V: FILTER_OUT:=0;
  signal W_DL: FILTER_OUT:=0;
  signal W_DR: FILTER_OUT:=0;
  signal RUN: STD_LOGIC:='0';
----------COMPONENT DECLARATIONS--------------
  component CLOCK_GENERATOR1
    port(RUN: in STD_LOGIC;
         CLOCK: out STD_LOGIC);  
  end component;
  component WINDOW_PROCESSOR1 
    port (CLOCK: in STD_LOGIC:='0';
          P1,P2,P3: in  PIXEL:=0;
          W_H: inout FILTER_OUT:=0;
          W_V: inout FILTER_OUT:=0;
          W_DL: inout FILTER_OUT:=0;
          W_DR: inout FILTER_OUT:=0 ); 
  end component;
begin
  L1: CLOCK_GENERATOR1
    port map(RUN,CLOCK);
  L2:WINDOW_PROCESSOR1
    port map(clock,P1,P2,P3,W_H,W_V,W_DL,W_DR);
  RUN<='0' after 0 ns, '1' after 5 ns, '0' after 1000 ns;
  P1<=  11 after 10 ns, 10 after 110 ns, 9 after 210 ns,
        12 after 310 ns,13 after 410 ns,48 after 510 ns;
  P2<=6 after 10 ns,  5 after 110 ns,14 after 210 ns,
     13 after 310 ns,10 after 410 ns,19 after 510 ns;
  P3<=8 after 10 ns,40 after 110 ns,  7 after 210 ns,
     10 after 310 ns,5 after 410 ns,110 after 510 ns;
end WINDOW_TB;

-- Figure 11.43
configuration WINDOW_BEH_INT of TB is
  for WINDOW_TB
    for L1:CLOCK_GENERATOR1
      use entity BEH_INT.CLOCK_GENERATOR(BEHAVIOR)
        generic map(HI_TIME=>75 ns,LO_TIME=>25 ns);
    end for;
    for L2: WINDOW_PROCESSOR1
      use STRUC_INT.WINDOW_PROCESSOR(BEHAVIOR)
        generic map(HORIZ_DELAY=>3 ns,
                    VERT_DELAY =>3 ns,
                    LEFT_DIAG_DELAY =>3 ns,
                    RIGHT_DIAG_DELAY =>3 ns,
                    WAIT_TIME=> 0 ns);
    end for;
  end for;
end;

-- Figure 11.44
configuration WINDOW_STRUC_INT of TB is
  for WINDOW_TB
    for L1:CLOCK_GENERATOR1
      use entity BEH_INT.CLOCK_GENERATOR(BEHAVIOR)
        generic map(HI_TIME=>75 ns,LO_TIME=>25 ns);
    end for;
    for L2: WINDOW_PROCESSOR1
      use configuration STRUC_INT.W_INT
        generic map(HORIZ_DELAY=>3 ns,
                    VERT_DELAY =>3 ns,
                    LEFT_DIAG_DELAY =>3 ns,
                    RIGHT_DIAG_DELAY =>3 ns,
                    WAIT_TIME=> 0 ns);
    end for;
  end for;
end;

-- Figure 11.45
configuration CONFIG_S2_INT of TB_CONFIG is
  for TEST_BENCH
    for con:TEST1 use entity BEH_INT.TEST(BENCH) 
      generic map("tesv_i2.dat", "test_o2.dat", 
                  "test_d2.dat", 10,10,5);
      for BENCH
        for P1:CLOCK_GENERATOR1 use entity 
               BEH_INT.CLOCK_GENERATOR(BEHAVIOR)
          generic map(HI_TIME=>75 ns,LO_TIME=>25 ns);
        end for;
        for P2:COMP_MAG1 use entity WORK.COMP_MAG(COMPARE)
          generic map("test_o2.dat","test_gm.dat",10,10);
        end for;
        for P3:COMP_DIR1 use entity WORK.COMP_DIR(COMPARE)
          generic map("test_d2.dat","test_gd.dat",10,10);
        end for;
        for P4:EDGE_DETECTOR1 use entity CONFIG_SOBEL_S_L2
          generic map(NUM_ROWS=>10,NUM_COLS=>10);
        end for;
      end for;
    end for;
  end for;
end;

-- Figure 11.46
library IEEE;
use ieee.std_logic_1164.all;
library STRUC_INT;
use STRUC_RTL.IMAGE_PROCESSING.all;  
-- interface declaration --------------------------
entity HORIZONTAL_FILTER is
  generic(HORIZ_DELAY: TIME; -- horizontal filter delay
          WAIT_TIME: TIME); -- abstraction level match
  port(CLOCK: in STD_LOGIC:='0';
       P1,P3: in PIXEL:=0; 
       H: inout FILTER_OUT:=0);
end HORIZONTAL_FILTER;
-- behavioral architecture declaration ------------
architecture BEHAVIOR of HORIZONTAL_FILTER is
  signal TEMP1: FILTER_OUT:=0;  -- intermediate signal 
begin
  H_FILTER: process
    variable TEMP_H: FILTER_OUT:=0;  -- temporary storage 
    variable FIRST_LINE: PIX3:=(0,0,0); -- first scan line
    variable THIRD_LINE: PIX3:=(0,0,0); -- third scan line
  begin
    wait until rising_edge(CLOCK);
--- store the input pixels in the 3-stage buffers ----
    FIRST_LINE:=SHIFT_LEFT(FIRST_LINE,P1);
    THIRD_LINE:=SHIFT_LEFT(THIRD_LINE,P3);
TEMP_H:=WEIGHT(FIRST_LINE(1),FIRST_LINE(2),FIRST_LINE(3))
     -WEIGHT(THIRD_LINE(1), THIRD_LINE(2), THIRD_LINE(3));
    TEMP1 <= TEMP_H after HORIZ_DELAY;
  end process H_FILTER;
---- make H as a delayed version of temp1 -------------
  H <= TEMP1 after WAIT_TIME; -- Horizontal filter output
end BEHAVIOR;

-- Figure 11.47
----- Weight function -----------------
function WEIGHT
   (X1,X2,X3: PIXEL)
    return FILTER_OUT is
begin
    return X1+ 2*X2 + X3;
end WEIGHT;



-- Figure 11.49
entity HORIZONTAL_FILTER is
  generic(HORIZ_DELAY:TIME);
  port(CLOCK: in STD_LOGIC:='0';
       P1,P3: in PIXEL:="00000000";
       H: inout STD_LOGIC_VECTOR(11 downto 0));
end HORIZONTAL_FILTER;
architecture STRUCTURE of HORIZONTAL_FILTER is
------ Empty component declarations --------
  component SUM12_PM     end component; -- Subtracter
  component REG12        end component; -- Register
  component SUM12_PP     end component; -- Adder
  component EXT8_12      end component; -- Extender
  component MULT_2_12_12 end component; -- Multiply by 2
---- intermediate signal declarations -------
  signal S1,S2,S3,S4,S5,S6,S7,A,B,C:
    STD_LOGIC_VECTOR(11 downto 0);
begin
----- empty component instantiations ---------
  EXT8_12A: EXT8_12;
  EXT8_12B: EXT8_12;
  DIFF1  : SUM12_PM;
  DELAY1 : REG12; 
  DELAY2 : REG12; 
  DELAY3 : REG12;
  SUM1   : SUM12_PP;
  DELAY4 : REG12;
  MULT_2_12_12A: MULT_2_12_12;
  SUM2   : SUM12_PP;
  DELAY5 : REG12;
end STRUCTURE;    

-- Figure 11.50
configuration H_RTL of HORIZONTAL_FILTER is
  for STRUCTURE
---------------- A <= "0000" & P1 ----------------
    for EXT8_12A:EXT8_12 use entity STRUC_RTL.EXT8_12(BEHAVIOR)
      port map(P1,A);
    end for;
---------------- B <= "0000" & P3 ----------------
    for EXT8_12B:EXT8_12 use entity STRUC_RTL.EXT8_12(BEHAVIOR)
      port map(P3,B);
    end for;
---------------- S1 <= A - B ---------------------
    for Diff1:SUM12_PM use entity STRUC_RTL.SUM12_PM(PARTS)
      port map(A,B,S1);
    end for;
------------------ S2 <= S1 ----------------
    for DELAY1:REG12 use entity STRUC_RTL.REG12(PARTS)
      generic map(HORIZ_DELAY)   
      port map( S1, S2, CLOCK );
    end for;
------------------ S3 <= S2 ----------------
    for DELAY2:REG12 use entity STRUC_RTL.REG12(PARTS)
      generic map(HORIZ_DELAY)   
      port map( S2, S3, CLOCK ); 
    end for;
------------------ S4 <= S3 ----------------
    for DELAY3:REG12 use entity STRUC_RTL.REG12(PARTS)
      generic map(HORIZ_DELAY)   
      port map( S3, S4, CLOCK ); 
    end for;
------------------ S5 <= S4 + S2 ----------------
    for SUM1:SUM12_PP use entity STRUC_RTL.SUM12_PP(PARTS)
      port map( S4, S2, S5 );
    end for;
------------------ S6 <= S5 ----------------
    for DELAY4:REG12 use entity STRUC_RTL.REG12(PARTS)
      generic map(HORIZ_DELAY)   
      port map( S5, S6, CLOCK ); 
    end for;

-- Figure 11.51
------------ C <= S4(10 downto 0) & '0' ----------------
    for MULT_2_12_12A:MULT_2_12_12 
      use entity STRUC_RTL.MULT_2_12_12(BEHAVIOR)
      port map(S4,C);
    end for;
----------------- S7 <= C + S6 -------------------------
    for SUM2:SUM12_PP use entity STRUC_RTL.SUM12_PP(PARTS)
      port map(C, S6, S7);
    end for;
------------------ H <= S7 ----------------
    for DELAY5:REG12 use entity STRUC_RTL.REG12(PARTS)
      generic map(HORIZ_DELAY)   
      port map( S7, H, CLOCK ); 
    end for;
  end for; -- End STRUCTURE.
end; -- End configuration.

-- Figure 11.52
entity WINDOW_PROCESSOR is
  generic(HORIZ_DELAY,VERT_DELAY,LEFT_DIAG_DELAY,
          RIGHT_DIAG_DELAY,WAIT_TIME: TIME);
  port(CLOCK: in std_logic:='0';  -- system CLOCK
       P1,P2,P3: in PIXEL:=0;     -- input Pixels
       W_H:  inout FILTER_OUT:=0; -- horizontal output
       W_V:  inout FILTER_OUT:=0; -- vertical output
       W_DL: inout FILTER_OUT:=0; -- left diagonal output
       W_DR: inout FILTER_OUT:=0);-- right diagonal output
end WINDOW_PROCESSOR;
architecture STRUCTURE of WINDOW_PROCESSOR is
------ empty component declarations------------------
  component HORIZONTAL_FILTER1 end component;
  component VERTICAL_FILTER1   end component;
  component LEFT_DIAG_FILTER1  end component;
  component RIGHT_DIAG_FILTER1 end component;
begin
------ empty component instantiations ---------------
  HP: HORIZONTAL_FILTER1;
  VP: VERTICAL_FILTER1; 
  LDP: LEFT_DIAG_FILTER1;
  RDP: RIGHT_DIAG_FILTER1; 
end STRUCTURE;

-- Figure 11.54
configuration WINDOW_H_RTL_OTHERS_INTEGER
              of WINDOW_PROCESSOR is
  generic map(HORIZ_DELAY=>3 ns, VERT_DELAY=>3 ns,
        LEFT_DIAG_DELAY=>3 ns,  RIGHT_DIAG_DELAY=>3 ns,
        WAIT_TIME=>0 ns)
  port map(CLOCK, MEM_OUT1, MEM_OUT2, MEM_OUT3,
           E_H, E_V, E_DL, E_DR);
  for structure
    for HP:HORIZONTAL_FILTER1
      use configuration STRUC_RTL.H_RTL
        generic map(HORIZ_DELAY=>HORIZ_DELAY)
        port map (CLOCKH=>CLOCK,
          P1H=>INT_TO_STDLOGIC8(P1),
          P3H=>INT_TO_STDLOGIC8(P3),
          STDLOGIC_TO_INT(H)=>INT_TO_STDLOGIC12(W_H));
    end for;
    for VP: VERTICAL_FILTER1 
      use entity STRUC_INT.VERTICAL_FILTER(BEHAVIOR)
        generic map(VERT_DELAY=>VERT_DELAY, 
                    WAIT_TIME=>WAIT_TIME)
        port map (CLOCK, P1, P2, P3, W_V);
    end for;
    for LDP: LEFT_DIAG_FILTER1 
      use entity STRUC_INT.LEFT_DIAG_FILTER(BEHAVIOR)
        generic map(LEFT_DIAG_DELAY=>LEFT_DIAG_DELAY,
                    WAIT_TIME=>WAIT_TIME)
        port map (CLOCK, P1, P2, P3, W_DL);
    end for;
    for RDP: RIGHT_DIAG_FILTER1 
      use entity STRUC_INT.RIGHT_DIAG_FILTER(BEHAVIOR)
        generic map(RIGHT_DIAG_DELAY=>RIGHT_DIAG_DELAY,
                    WAIT_TIME=>WAIT_TIME)
        port map (CLOCK, P1, P2, P3, W_DR);
    end for;
  end for;
end;