chapter11_models.vhd

James Armstrong VHDL Design , source code

	num_cols	:natural;         -- number of columns in the input image

	wait_cycles	:natural);        -- time required before outputs are 
				          -- written into frame buffers.
end test;

architecture bench of test is

type frame_image is array(1 to num_rows,1 to num_cols) of integer;
type frame_direction is array(1 to num_rows,1 to num_cols) of bit_vector(2 downto 0);

component Clock_Generator1 
	port(  RUN : in std_logic;
        Clock: out Std_logic);  
 end component ;

 component edge_detector1 
    port (Clock: in Std_logic;
	  edge_start : in std_logic;
          input: in pixel;
          output: inout pixel;
          dir: inout direction);
end component;

component comp_mag1
	port(clock : in std_logic;
	     start : in std_logic:='0'
       	    );
end component;

component comp_dir1
	port(clock : in std_logic;
	     start : in std_logic:='0'
	    );
end component;
  
signal RUN	: std_logic:='0';
signal Clock	: std_logic:='0';
signal start	: std_logic:='0';
signal input, output: pixel;
signal dir	: direction;
signal RD_Start: std_logic:='0';
signal comp_start : std_logic:='0';

begin

Start<='0' after 0 ns,'1' after 5 ns,'0' after 105 ns;

P1 : Clock_Generator1
port map(Run,Clock);

P2 : Comp_mag1
port map(Clock,Comp_Start);

P3 : Comp_dir1
port map(Clock,Comp_Start);

P4 :edge_detector1
port map(Clock,RD_start,Input,Output,Dir);



Clock1 : process
begin

Run<=transport '1' after 0 ns,'0' after 100000000 ns;
wait;
end process;

Memory1: process

variable vline1,vline2,vline3:line; -- for reading and writing from the input
				    -- and output text files

variable busy:integer range 0 to 3;  -- internal variable to trigger the differnt parts
				    -- of the test bench
variable busy1,busy2,busy3:std_logic:='0'; --internal busy signals
variable input_image : frame_image; 	-- frame buffer to store input image data
variable output_mag_image : frame_image;-- frame buffer to store magnitude outputs
variable output_dir_image : frame_direction;-- frame buffer to store the direction outputs
variable a,b,c,z   : integer;          	-- used for reading and writing the input and
				       	-- output files
variable i,j:natural:=1;              	-- used for indexing the frame buffers
variable x,y:natural:=2;              	-- used for indexing the frame buffers
variable count:integer:=0;            	-- used to specify when the outputs can be
				      	-- written into the buffers

-----------------------------------------------------------------------------------
--FILES--

file imagein	:TEXT is in in_file;   	--input image file
file imageout	:TEXT is out out_file; 	--output file for storing magnitude outputs
file dirout	:TEXT is out dir_file;  --output file which stores direction outputs
					  	
       

begin  
   wait until rising_edge(Clock);    
   -- set the internal busy signal
      	if start = '1' then
          busy :=1;
          count:=0;
          i:=1;
          j:=1;
          x:=2;
   	  y:=2;
	end if;

case busy is 
when 1 =>
-- load the image data file to the memory array B
          for i in 1 to num_rows loop
            readline(imagein,vline1);
            for j in 1 to num_cols loop
	      read(vline1,z);
              input_image(i,j):= z;
              output_mag_image(i,j):=0;
 	      output_dir_image(i,j):="000";
	    end loop;
          end loop;
	  busy:=2;
     -- assert message after loading all the data
        assert (false) report "array read in";

when 2 =>  

	count:=count+1; 
		input <= (input_image(i,j));
		if (i=1) and (j=1) then 
			RD_Start<='1';
		else
			RD_Start<='0';
		end if;					
		if (i=num_rows) and (j=num_cols) then
			i:=1;
			j:=1;
 	   	elsif j=num_cols then
			j:=1;
			i:=i+1;
	   	else
	   		j:=j+1;
	   	end if; 

	-- write the data out to a file 
        
	if count>=(2*num_cols+wait_cycles) then
		if not(y=1) and not(y=num_cols)  then        
	      		output_mag_image(x,y):= Output;
	      		output_dir_image(x,y) := Dir;
	      	end if; 
	      	y:=y+1;
	      	if y=num_cols+1 then
	      		y:=1;
	      		x:=x+1;
	      	end if;	
	      
              	if (x=num_rows-1) and y=num_cols then
	      		busy:=3;
	      	end if;		
 	      
	end if;
	
when 3 =>  
	RD_start<='0';
		for i in 1 to num_rows loop
           	for j in 1 to num_cols loop
                	write(vline1,output_mag_image(i,j));
              		write(vline1,' ');
                	write(vline2,output_dir_image(i,j));
			write(vline2,' ');
            	end loop;
            		writeline(imageout,vline1); 
     	    		writeline(dirout,vline2);        
         	end loop;
         -- assert message after loading all the data
         assert (false) report "magnitude and direction outputs written to file";
        Comp_Start<='1';
        busy:=0;

when others => null;
       end case; 
end process Memory1;
end bench;

-- Magnitude Comparator Element
-- Figures 11.28 and 11.29
library IEEE;
use ieee.std_logic_1164.all;
use std.textio.all;

entity comp_mag is
	generic(mag_file,gold_file:string(1 to 11);
	        num_rows,num_cols : natural);
	port(clock : in std_logic;
	     start : in std_logic:='0'
	     );
end comp_mag;

architecture compare of comp_mag is
type frame_image is array(1 to num_rows,1 to num_cols) of integer;

signal end_comp_mag :std_logic:='0';

begin

--Compare the magnitude output of the MUT 
--with the magnitude output of the "GOLD MODEL--  

process

variable flag1,busy: std_logic:='0';
variable a,b: integer;
variable vline1,vline2:line;
variable test_mag_image,gold_mag_image : frame_image;


--FILES :

file test_magnitude : TEXT is mag_file;
file gold_magnitude : TEXT is gold_file;

begin

wait until rising_edge(clock);
if start ='1' then
if end_comp_mag ='0' then
busy:='1';
end if;
end if;
 
 if busy='1' then
	  for i in 1 to num_rows loop
            readline(test_magnitude,vline1);
	    readline(gold_magnitude,vline2);
	    for j in 1 to num_cols loop
              read(vline1,a);
	      read(vline2,b);
                test_mag_image(i,j):=a;
	        gold_mag_image(i,j):=b;
		if flag1='0' then
                if test_mag_image(i,j) /= gold_mag_image(i,j) then
                 --set flag high--
                flag1:='1';
                end if;
              end if;
      end loop;
end loop;



if flag1='1' then
-- assert message after comparing all the data
          assert (false) report "MAGNITUDE VALUES DO NOT MATCH -- FAIL";
            else
          assert (false) report "MAGNITUDE VALUES MATCH -- PASS";
end if;
end_comp_mag<='1';
end if;
busy:='0';

end process;
end compare;

-- Direction Comparator Element
library IEEE;
use ieee.std_logic_1164.all;
use std.textio.all;

entity comp_dir is
generic(dir_file,gold_file:string(1 to 11);
	num_rows,num_cols : natural);
port(clock : in std_logic;
     start : in std_logic:='0'
    );
end comp_dir;

architecture compare of comp_dir is

type frame_image is array(1 to num_rows,1 to num_cols) of integer;

signal end_comp_dir : std_logic:='0';
begin

--Compare the direction output of the MUT 
--with the direction output of the "GOLD MODEL--  

process

variable flag1,busy: std_logic:='0';
variable a,b: integer;
variable vline1,vline2:line;
variable test_dir_image,gold_dir_image : frame_image;


--FILES :

file test_direction : TEXT is dir_file;
file gold_direction : TEXT is gold_file;

begin
 
wait until rising_edge(clock);
if start ='1' then
if end_comp_dir='0' then
busy:='1';
end if;
end if;

if busy ='1' then
	  for i in 1 to num_rows loop
            readline(test_direction,vline1);
	    readline(gold_direction,vline2);
	    for j in 1 to num_cols loop
              read(vline1,a);
	      read(vline2,b);
                test_dir_image(i,j):=a;
	        gold_dir_image(i,j):=b;
		if flag1='0' then
                if test_dir_image(i,j) /= gold_dir_image(i,j) then
                 --set flag high--
                flag1:='1';
                end if;
              end if;
      end loop;
end loop;
if flag1='1' then
-- assert message after comparing all the data
          assert (false) report "DIRECTION VALUES DO NOT MATCH -- FAIL";
            else
          assert (false) report "DIRECTION VALUES MATCH -- PASS";
          end if;
end_comp_dir<='1';
end if;
busy:='0';

end process;
end compare;

-- Figure 11.30, 11.31
--declaration of an empty top level component--
entity TB_CONFIG is
end TB_CONFIG;

architecture TEST_BENCH of TB_CONFIG is
  component TEST1
  end component;

begin
  con: TEST1;
end TEST_BENCH;

---CONFIGURATION DECLARATION---------
library IEEE;
use ieee.STD_LOGIC_1164.all;

library BEH_INT;
use BEH_INT.IMAGE_PROCESSING.all;
use BEH_INT.all;
use STD.TEXTIO.all;

configuration CONFIG_B_INT of TB_CONFIG is
  for TEST_BENCH
    for con:TEST1 use entity BEH_INT.TEST(BENCH) 
      generic map("tesv_i2.dat", "test_o1.dat",
                  "test_d1.dat", 10,10,5);

      for BENCH
        for P1:CLOCK_GENERATOR1 use entity 
          BEH_INT.CLOCK_GENERATOR(BEHAVIOR)
          generic map(HI_TIME=>75 ns,LO_TIME=>25 ns);
        end for;

        for P2:COMP_MAG1 use entity
          BEH_INT.COMP_MAG(COMPARE)
          generic map("test_o1.dat","test_gm.dat",10,10);
        end for;

        for P3:COMP_DIR1 use entity BEH_INT.COMP_DIR(COMPARE)
          generic map("test_d1.dat","test_gd.dat",10,10);
        end for;

        for P4:EDGE_DETECTOR1 use entity
          BEH_INT.EDGE_DETECTOR(BEHAVIOR)
          generic map(NUM_ROWS=>10,NUM_COLS=>10);
        end for;
      end for;  -- End of BENCH
    end for;    -- End of con:TEST1
  end for;      -- End TEST_BENCH
end;            -- End of configuration

-- Figure 11.36, 11.37
-- structural description of edge detector ---
architecture STRUCTURE of EDGE_DETECTOR is

  -- memory processor component declaration --
  component MEMORY_PROCESSOR1
    generic (NUM_ROWS, NUM_COLS: NATURAL;
             MEM_OUT_DELAY:TIME)
    port(CLOCK: in STD_LOGIC:='0';   -- system CLOCK
         START: in STD_LOGIC:='0';   -- start signal 
         MEM_IN: in PIXEL:=0;        -- input pixel
         MEM_OUT1, MEM_OUT2, MEM_OUT3: inout PIXEL:=0);
  end component; 

-- window processor component declaration --
  component WINDOW_PROCESSOR1
    generic(HORIZ_DELAY, VERT_DELAY, LEFT_DIAG_DELAY,
            RIGHT_DIAG_DELAY, WAIT_TIME:TIME)
    port(CLOCK: in STD_LOGIC:='0';  -- system CLOCK
        P1,P2,P3: in PIXEL:=0;     -- input pixels
        W_H: inout FILTER_OUT:=0;  -- horizontal filter
        W_V: inout FILTER_OUT:=0;  -- vertical filter
        W_DL: inout FILTER_OUT:=0; -- left diagonal filter
        W_DR: inout FILTER_OUT:=0);-- right diagonal filter
  end component; 

-- magnitude processor component declaration --
  component MAG_PROCESSOR1
    generic(MAG_DELAY: TIME); -- magnitude processor delay
    port(CLOCK: in STD_LOGIC:='0';  -- system CLOCK
         M_H,M_V,M_DL,M_DR: in FILTER_OUT:=0;  -- filter
           -- values from the window processor
         THRESHOLD: in FILTER_OUT:=0;  -- threshold value