📄 chapter11_rtl_package.vhd
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-- file name: rtl_pack.vhd
-- purpose: define the basic components (half_adder, full_adder, sum12_pp,
-- full_substractor, sum12_pm, reg1,reg3,
-- reg8, reg12, mux1_by2, Mux12_by_2,
-- abs12,reg_angle, compare_GE)
--------------------------------------------------------------------------------
-- **************
-- * Half_Adder *
-- **************
library IEEE;
use IEEE.std_logic_1164.all;
entity Half_Adder is
port(
A, B : in std_logic:='0';
Y, Cout : out std_logic:='0'
);
end Half_Adder;
architecture DataFlow of Half_Adder is
begin
Y <= A xor B;
Cout <= A and B;
end DataFlow;
-----------------------------------------------------------------------------
-- **************
-- * Full_Adder *
-- **************
library IEEE;
use ieee.std_logic_1164.all;
entity Full_Adder is
port(A, B, Cin : in std_logic:='0';
Sum, Cout : out std_logic:='0');
end Full_Adder;
architecture DataFlow of Full_Adder is
begin
Sum <= A xor B xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);
end DataFlow;
-----------------------------------------------------------------------------
-- *********************
-- * 12-bit Full_Adder *
-- *********************
library IEEE;
use ieee.std_logic_1164.all;
library STRUC_RTL;
use STRUC_RTL.all;
entity Sum12_PP is
port(Arg1 : in std_logic_vector(11 downto 0):="000000000000";
Arg2 : in std_logic_vector(11 downto 0):="000000000000";
Result : out std_logic_vector(11 downto 0):="000000000000");
end Sum12_PP;
architecture Parts of Sum12_PP is
component Full_Adder
port(A, B, Cin : in std_logic:='0';
Sum, Cout : out std_logic:='0');
end component;
for all : Full_Adder use entity STRUC_RTL.Full_Adder(DataFlow);
signal C0, C1, C2, C3, C4, C5, C6, C7,
C8, C9, C10, C11, C12 :std_logic:='0';
begin
C0 <= '0';
Fa0 : Full_Adder port map( Arg1( 0), Arg2( 0), C0, Result( 0), C1 );
Fa1 : Full_Adder port map( Arg1( 1), Arg2( 1), C1, Result( 1), C2 );
Fa2 : Full_Adder port map( Arg1( 2), Arg2( 2), C2, Result( 2), C3 );
Fa3 : Full_Adder port map( Arg1( 3), Arg2( 3), C3, Result( 3), C4 );
Fa4 : Full_Adder port map( Arg1( 4), Arg2( 4), C4, Result( 4), C5 );
Fa5 : Full_Adder port map( Arg1( 5), Arg2( 5), C5, Result( 5), C6 );
Fa6 : Full_Adder port map( Arg1( 6), Arg2( 6), C6, Result( 6), C7 );
Fa7 : Full_Adder port map( Arg1( 7), Arg2( 7), C7, Result( 7), C8 );
Fa8 : Full_Adder port map( Arg1( 8), Arg2( 8), C8, Result( 8), C9 );
Fa9 : Full_Adder port map( Arg1( 9), Arg2( 9), C9, Result( 9), C10);
Fa10 : Full_Adder port map( Arg1(10), Arg2(10), C10, Result(10), C11);
Fa11 : Full_Adder port map( Arg1(11), Arg2(11), C11, Result(11), C12);
end Parts;
-----------------------------------------------------------------------------
-- *******************
-- * Full_Subtractor *
-- *******************
library IEEE;
use ieee.std_logic_1164.all;
entity Full_Subtractor is
port(A, B, Bin : in std_logic:='0';
Diff, Bout: out std_logic:='0');
end Full_Subtractor;
architecture DataFlow of Full_Subtractor is
begin
Diff <= A xor B xor Bin;
Bout <= (not(A) and B) or (B and Bin) or (not(A) and Bin);
end DataFlow;
------------------------------------------------------------------------------
-- **************************
-- * 12-bit Full_Subtractor *
-- **************************
library IEEE;
use ieee.std_logic_1164.all;
library STRUC_RTL;
use STRUC_RTL.all;
entity Sum12_PM is
port(Arg1 : in std_logic_vector(11 downto 0):="000000000000";
Arg2 : in std_logic_vector(11 downto 0):="000000000000";
Result : out std_logic_vector(11 downto 0):="000000000000");
end Sum12_PM;
architecture Parts of Sum12_PM is
component Full_Subtractor
port(A, B, Bin : in std_logic:='0';
Diff, Bout : out std_logic:='0');
end component;
for all : Full_Subtractor use entity STRUC_RTL.Full_Subtractor(DataFlow);
signal C0, C1, C2, C3, C4, C5, C6,
C7, C8, C9, C10, C11, C12 : std_logic:='0';
begin
C0 <= '0';
Fs0 : Full_Subtractor port map( Arg1( 0), Arg2( 0), C0, Result( 0), C1 );
Fs1 : Full_Subtractor port map( Arg1( 1), Arg2( 1), C1, Result( 1), C2 );
Fs2 : Full_Subtractor port map( Arg1( 2), Arg2( 2), C2, Result( 2), C3 );
Fs3 : Full_Subtractor port map( Arg1( 3), Arg2( 3), C3, Result( 3), C4 );
Fs4 : Full_Subtractor port map( Arg1( 4), Arg2( 4), C4, Result( 4), C5 );
Fs5 : Full_Subtractor port map( Arg1( 5), Arg2( 5), C5, Result( 5), C6 );
Fs6 : Full_Subtractor port map( Arg1( 6), Arg2( 6), C6, Result( 6), C7 );
Fs7 : Full_Subtractor port map( Arg1( 7), Arg2( 7), C7, Result( 7), C8 );
Fs8 : Full_Subtractor port map( Arg1( 8), Arg2( 8), C8, Result( 8), C9 );
Fs9 : Full_Subtractor port map( Arg1( 9), Arg2( 9), C9, Result( 9), C10);
Fs10 : Full_Subtractor port map( Arg1(10), Arg2(10), C10, Result(10), C11);
Fs11 : Full_Subtractor port map( Arg1(11), Arg2(11), C11, Result(11), C12);
end Parts;
--------------------------------------------------------------------------------
-- ******************
-- * 1-bit register *
-- ******************
library IEEE;
use ieee.std_logic_1164.all;
entity Reg1 is
generic(reg_delay:time);
port(
Input : in std_logic:='0';
Output : out std_logic:='0';
Strobe : in std_logic:='0'
);
end Reg1;
architecture Behave of Reg1 is
begin
process(Strobe)
begin
if Strobe'event and Strobe='1' then
Output <= Input;-- after reg_delay;
end if;
end process;
end Behave;
--------------------------------------------------------------------------------
-- ******************
-- * 3-bit register *
-- ******************
library IEEE;
use ieee.std_logic_1164.all;
library STRUC_RTL;
use STRUC_RTL.all;
entity Reg3 is
generic(angle_delay:time);
port(Inputs : in std_logic_vector(2 downto 0):="000";
Outputs : out std_logic_vector(2 downto 0):="000";
Strobe : in std_logic:='0');
end Reg3;
architecture parts of Reg3 is
component Reg1
generic(reg_delay:time);
port(Input : in std_logic:='0';
Output : out std_logic:='0';
Strobe : in std_logic:='0');
end component;
for all : Reg1 use entity STRUC_RTL.Reg1(Behave);
begin
RA_1 : Reg1 generic map(angle_delay)
port map(inputs(0),outputs(0),strobe);
RA_2 : Reg1 generic map(angle_delay)
port map(inputs(1),outputs(1),strobe);
RA_3 : Reg1 generic map(angle_delay)
port map(inputs(2),outputs(2),strobe);
end parts;
--------------------------------------------------------------------------------
-- ******************
-- * 8-bit register *
-- ******************
library IEEE;
use ieee.std_logic_1164.all;
library STRUC_RTL;
use STRUC_RTL.all;
entity Reg8 is
generic(reg_delay:time);
port(Inputs : in std_logic_vector(7 downto 0):="00000000";
Outputs : out std_logic_vector(7 downto 0):="00000000";
Strobe : in std_logic:='0');
end Reg8;
architecture parts of Reg8 is
component Reg1
generic(reg_delay:time);
port(
Input : in std_logic:='0';
Output : out std_logic:='0';
Strobe : in std_logic:='0'
);
end component;
for all : Reg1 use entity STRUC_RTL.Reg1(Behave);
begin
R8_1 : Reg1 generic map(reg_delay)
port map(inputs(0),outputs(0),strobe);
R8_2 : Reg1 generic map(reg_delay)
port map(inputs(1),outputs(1),strobe);
R8_3 : Reg1 generic map(reg_delay)
port map(inputs(2),outputs(2),strobe);
R8_4 : Reg1 generic map(reg_delay)
port map(inputs(3),outputs(3),strobe);
R8_5 : Reg1 generic map(reg_delay)
port map(inputs(4),outputs(4),strobe);
R8_6 : Reg1 generic map(reg_delay)
port map(inputs(5),outputs(5),strobe);
R8_7 : Reg1 generic map(reg_delay)
port map(inputs(6),outputs(6),strobe);
R8_8 : Reg1 generic map(reg_delay)
port map(inputs(7),outputs(7),strobe);
end parts;
-------------------------------------------------------------------------------
-- *******************
-- * 12-bit register *
-- *******************
library IEEE;
use ieee.std_logic_1164.all;
library STRUC_RTL;
use STRUC_RTL.all;
entity Reg12 is
generic(reg_delay:time);
port(Inputs : in std_logic_vector(11 downto 0):="000000000000";
Outputs : out std_logic_vector(11 downto 0):="000000000000";
Strobe : in std_logic:='0');
end Reg12;
architecture parts of Reg12 is
component Reg1
generic(reg_delay:time);
port(
Input : in std_logic:='0';
Output : out std_logic:='0';
Strobe : in std_logic:='0'
);
end component;
for all : Reg1 use entity STRUC_RTL.Reg1(Behave);
begin
R12_1 : Reg1 generic map(reg_delay)
port map(inputs(0),outputs(0),strobe);
R12_2 : Reg1 generic map(reg_delay)
port map(inputs(1),outputs(1),strobe);
R12_3 : Reg1 generic map(reg_delay)
port map(inputs(2),outputs(2),strobe);
R12_4 : Reg1 generic map(reg_delay)
port map(inputs(3),outputs(3),strobe);
R12_5 : Reg1 generic map(reg_delay)
port map(inputs(4),outputs(4),strobe);
R12_6 : Reg1 generic map(reg_delay)
port map(inputs(5),outputs(5),strobe);
R12_7 : Reg1 generic map(reg_delay)
port map(inputs(6),outputs(6),strobe);
R12_8 : Reg1 generic map(reg_delay)
port map(inputs(7),outputs(7),strobe);
R12_9 : Reg1 generic map(reg_delay)
port map(inputs(8),outputs(8),strobe);
R12_10 :Reg1 generic map(reg_delay)
port map(inputs(9),outputs(9),strobe);
R12_11 :Reg1 generic map(reg_delay)
port map(inputs(10),outputs(10),strobe);
R12_12 :Reg1 generic map(reg_delay)
port map(inputs(11),outputs(11),strobe);
end parts;
--------------------------------------------------------------------------------
-- ****************************
-- * 1-bit 2-to-1 Multiplexer *
-- ****************************
library IEEE;
use ieee.std_logic_1164.all;
entity Mux1_by_2 is
port(
A, B : in std_logic:='0';
Result : out std_logic:='0';
Select_B : in std_logic:='0'
);
end Mux1_by_2;
architecture Behave of Mux1_by_2 is
begin
process( A, B, Select_B )
begin
if (Select_B = '1') then
Result <= B;
elsif (Select_B = '0') then
Result <= A;
else
Result <= 'U';
end if;
end process;
end Behave;
--------------------------------------------------------------------------------
-- ****************************
-- * 8-bit 2-to-1 Multiplexer *
-- ****************************
library IEEE;
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