chapter7_models.vhd

James Armstrong VHDL Design , source code

  component OSC
    port(RUN: in BIT; CLOCK: out BIT := '0');
  end component;
  component UP_CNT
    port(RESET,COUNT,CLK: in BIT;
         CNT: inout BIT_VECTOR(2 downto 0));
  end component;
begin
  C0: OSC
    port map(RUN => RUN,CLOCK => CLK);
  C1: UP_CNT
    port map(RESET => RESET, COUNT=> COUNT,
             CLK => CLK, CNT => CNT);
end STRUCTB;
--Figure 7.40 Unbound structural architecture of counter system.

entity UP_CNT is
  generic(R_DEL,CLK_DEL:TIME);
  port(RESET,COUNT,CLK: in BIT;
       CNT: inout BIT_VECTOR(2 downto 0));
end UP_CNT;
architecture STRUCT of UP_CNT is
  signal C01: BIT;
  component T
    port(R,T,CLK: in BIT; Q: out BIT);
  end component;
  component AND2G
    port(I1,I2: in BIT; O: out BIT);
  end component;
begin
  C1: T
    port map(R => RESET,T => COUNT,CLK => CLK,Q => CNT(0));
  C2: T
    port map(R => RESET,T => CNT(0),CLK => CLK,Q => CNT(1));
  C3: T
    port map(R => RESET,T => C01, CLK => CLK, Q => CNT(2));
  C4: AND2G
    port map(I1 => CNT(0), I2 => CNT(1), O => C01);
end STRUCT;
--Figure 7.41 Unbound structural architecture of UP counter.

configuration ALL_BEHAV of CTR is
  for STRUCTB
    for C0: OSC use entity work.COSC(WAIT_DEL)
      generic map(60 ns, 40 ns);
    end for;
    for C1: UP_CNT use entity work.UP_CNT(ALG)
      generic map(10 ns, 15 ns);
    end for;
  end for;
end ALL_BEHAV;
--Figure 7.42 Behavioral configuration of counter system.

configuration PART_STRUCT of CTR is
  for STRUCTB
    for C0: OSC use entity work.COSC(WAIT_DEL)
      generic map(60 ns, 40 ns);
    end for;
    for C1: UP_CNT use entity work.UP_CNT(STRUCT)
      generic map(10 ns, 15 ns);
        for STRUCT
          for all: T use entity work.TFF(ALG)
            generic map(10 ns, 15 ns);
          end for;
          for C4: AND2G use entity work.AND2(BEH)
            generic map(5 ns);
          end for;
        end for;
    end for;
  end for;
end PART_STRUCT;
--Figure 7.43 Partly structural configuration of counter system.

entity BUFF is
  port( I: in BIT; O: out BIT);
end BUFF;
architecture ALG of BUFF is
begin
  O <= I;
end ALG;
(a) Behavioral Buffer

entity INV is
  port(I: in BIT; O: out BIT);
end INV;
architecture ALG of INV is
begin
  O <= not I;
end ALG;  

entity BUFF is
  port( I: in BIT; O: out BIT);
end BUFF;

architecture STRUCTURE of BUFF is
  component INV 
    port(I: in BIT; O: out BIT);
  end component;
  signal S: BIT;
begin
  C1: INV
    port map(I,S);
  C2 : INV
    port map(S,O);
end STRUCTURE;

(b) Structural Buffer
--Figure 7.44 Default configuration for behavioral and structural buffers.

entity TB is
end TB;

architecture BUF_TEST of TB is
  signal I,O: BIT;
  component BUFF
    port( I: in BIT; O: out BIT);
  end component;
begin
  C1: BUFF
    port map(I,O);
  I <= '0', '1' after 10 ns, '0' after 20 ns;
end BUF_TEST;
configuration DEFAULT_1 of TB is
  for BUF_TEST
    for C1:BUFF
    end for;
  end for;
end DEFAULT_1;
--Figure 7.45  Default configuration for testbench

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_entities.all;
use work.all;
entity TWO_CONSECUTIVE is
  port(CLK, R: in STD_LOGIC; X: in STD_LOGIC;
            Z: out STD_LOGIC);
end TWO_CONSECUTIVE;

architecture STRUCTURAL of TWO_CONSECUTIVE is
  signal Y0, Y1, A0, A1: STD_LOGIC:= '0';
  signal NY0, NX: STD_LOGIC:= '1';
  signal ONE: STD_LOGIC:= '1';
  component EDGE_TRIGGERED_D
    port(CLK, D, NCLR: in STD_LOGIC; Q, QN: out STD_LOGIC);
  end component;
---------------- edge triggered register -------------
  component INVG
    port(I: in STD_LOGIC; O: out STD_LOGIC);
  end component;
---------------------- inverter ----------------------
  component AND3G
    port(I1, I2, I3: in STD_LOGIC; O: out STD_LOGIC);
  end component;
---------------------- ANDGATE -----------------------
  component OR2G
    port(I1, I2: in STD_LOGIC; O: out STD_LOGIC);
  end component;
----------------------- ORGATE -----------------------
begin
  C1: EDGE_TRIGGERED_D
    port map(CLK, X, R, Y0, NY0);
  C2: EDGE_TRIGGERED_D
    port map(CLK, ONE, R, Y1, open);
  C3: INVG
    port map(X, NX);
  C4: AND3G
    port map(X, Y0, Y1, A0);
  C5: AND3G
    port map(NY0, Y1, NX, A1);
  C6: OR2G
    port map(A0, A1, Z);
end STRUCTURAL;
--Figure 7.46 TWO_CONSECUTIVE structural model.

configuration PARTS1 of TWO_CONSECUTIVE is
  for STRUCTURAL
    for all: EDGE_TRIGGERED_D use entity work.DFFREG(A)
      port map(Clock => CLK, Data(0) => D, Reset => NCLR,
                        Output(0) => Q, Noutput(0)=> QN);
    end for;
    for all: INVG use entity INVGATE(A)
      port map(Input => I, Output => O);
    end for;
    for all: AND3G use entity ANDGATE(A)
      generic map(N => 3)
      port map(Input(1) => I1, Input(2) => I2,
               Input(3) => I3, Output => O);
    end for;
    for all: OR2G use entity ORGATE(A)
      generic map(N => 2)
      port map(Input(1) => I1, Input(2) => I2, Output => O);
    end for;
  end for;
end PARTS1;

configuration PARTS2 of TWO_CONSECUTIVE is
  for STRUCTURAL
    for all: EDGE_TRIGGERED_D use entity work.DFFREG(A)
      generic map(TLH=> 5 ns, THL=> 6 ns)
      port map(Clock => CLK, Data(0) => D, Reset => NCLR,
                        Output(0) => Q, Noutput(0)=> QN);
    end for;
    for all: INVG use entity INVGATE(A)
      generic map(TLH=> 1 ns, THL=> 2 ns) 
      port map(Input => I, Output => O);
    end for;
    for all: AND3G use entity ANDGATE(A)
      generic map(N => 3, TLH=> 3 ns, THL=> 4 ns)
      port map(Input(1) => I1, Input(2) => I2,
               Input(3) => I3, Output => O);
    end for;
    for all: OR2G use entity ORGATE(A)
      generic map(N => 2, TLH=> 2 ns, THL=> 3 ns)
      port map(Input(1) => I1, Input(2) => I2, Output => O);
    end for;
  end for;
end PARTS2;
--Figure 7.48 Two configurations binding to library components.

configuration FAST of CTR is
  for STRUCTB
    for C0: OSC use entity work.COSC(WAIT_DEL)
      generic map(11 ns, 10 ns);
    end for;
    for C1: UP_CNT use entity work.UP_CNT(STRUCT)
      generic map(10 ns, 15 ns);
      for STRUCT
        for all: T use entity work.TFF(ALG)
          generic map(10 ns, 15 ns);
        end for;
        for C4: AND2G use entity work.AND2(BEH)
          generic map(5 ns);
        end for;
      end for;
    end for;
  end for;
end FAST;

configuration TOO_FAST of CTR is
  for STRUCTB
    for C0: OSC use entity work.COSC(WAIT_DEL)
      generic map(10 ns, 9 ns);
    end for;
    for C1: UP_CNT use entity work.UP_CNT(STRUCT)
      generic map(10 ns, 15 ns);
      for STRUCT
        for all: T use entity work.TFF(ALG)
          generic map(10 ns, 15 ns);
        end for;
        for C4: AND2G use entity work.AND2(BEH)
          generic map(5 ns);
        end for;
      end for;
    end for;
  end for;
end TOO_FAST;
--Figure 7.51Configurations used to model race conditions.

library SYNOPSYS;
use SYNOPSYS.TYPES.all;
entity RGLITCH is
  port(A,B,C,I,CLK: in MVL7; Q: out MVL7);
end RGLITCH;
architecture STRUCT of RGLITCH is
  signal A1,A2,NB,R : MVL7;
  component DFF
    port(R,CLK,D: in MVL7; Q: out MVL7);
  end component;
  component AND2
    port(I1,I2: in MVL7; O: out MVL7);
  end component;
  component OR2
    port(I1,I2: in MVL7; O: out MVL7);
  end component;
  component INV
    port(I: in MVL7; O: out MVL7);
  end component;
begin
  C1: AND2
    port map(I1 => A, I2  => B, O => A1);
  C2: AND2
    port map(I1 => NB, I2 => C, O => A2);
  C3: OR2
    port map(I1 => A1, I2 => A2, O => R);
  C4: INV
    port map(I => C, O => NB);
  C5: DFF
    port map(R => R, CLK => CLK, D => I, Q => Q);
end STRUCT;
--Figure 7.53 An unbound structural architecture.

configuration GLTCH of RGLITCH is
  for STRUCT
    for all: DFF use entity WORK.DFFREG(A)
      generic map(TLH => 5 ns, THL => 6 ns)
      port map(CLOCK => CLK, DATA(0) => D, RESET => R,
               OUTPUT(0) => Q);
    end for;
    for all: INV use entity SYNOPSYS.INVGATE(A)
      generic map(TLH => 2 ns, THL => 3 ns)
      port map(INPUT => I, OUTPUT => O);
    end for;
    for C1 : AND2 use entity SYNOPSYS.ANDGATE(A)
      generic map(N => 2, TLH => 2 ns, THL => 3 ns)
      port map(INPUT(1) => I1, INPUT(2) => I2, OUTPUT => O);
    end for;
    for C2 : AND2 use entity SYNOPSYS.ANDGATE(A)
      generic map(N => 2, TLH => 4 ns, THL => 5 ns)
      port map(INPUT(1) => I1, INPUT(2) => I2, OUTPUT => O);
    end for;
    for all: OR2 use entity SYNOPSYS.ORGATE(A)
      generic map(N => 2, TLH => 2 ns, THL => 3 ns)
      port map(INPUT(1) => I1, INPUT(2) => I2, OUTPUT => O);
    end for;
  end for;
end GLTCH;
--Figure 7.54 A glitch producing configuration.

configuration GLTCH2 of RGLITCH is
  for STRUCT
    for all: DFF use entity WORK.DFFREG(A)
      generic map(TLH => 5 ns, THL => 6 ns)
      port map(CLOCK => CLK, DATA(0) => D, RESET => R,
               OUTPUT(0) => Q);
    end for;
    for all: INV use entity SYNOPSYS.INVGATE(A)
      generic map(TLH => 2 ns, THL => 3 ns)
      port map(INPUT => I, OUTPUT => O);
    end for;
    for C1 : AND2 use entity SYNOPSYS.ANDGATE(A)
      generic map(N => 2, TLH => 4 ns, THL => 5 ns)
      port map(INPUT(1) => I1,INPUT(2) => I2,OUTPUT => O);
    end for;
    for C2 : AND2 use entity SYNOPSYS.ANDGATE(A)
      generic map(N => 2, TLH => 1 ns, THL => 2 ns)
      port map(INPUT(1) => I1,INPUT(2) => I2, OUTPUT => O);
    end for;
    for all: OR2 use entity SYNOPSYS.ORGATE(A)
      generic map(N => 2, TLH => 1 ns, THL => 2 ns)
      port map(INPUT(1) => I1,INPUT(2) => I2, OUTPUT => O);
    end for;
  end for;
end GLTCH2;
--Figure 7.56 Another glitch producing configuration.

entity  OR2G is
  generic(DEL: TIME);
  port(I1,I2: in BIT; O: out BIT);
end OR2G;
architecture GNR_DEL of OR2G is
begin
  O <= I1 or I2 after DEL;
end GNR_DEL;

entity  AND2G is
  generic(DEL: TIME);
  port(I1,I2: in BIT; O: out BIT);
end AND2G;
architecture GNR_DEL of AND2G is
begin
  O <= I1 and I2 after DEL;
end GNR_DEL;

entity THREE_GATES is
  generic(GATE_DEL: TIME:= 2 ns);
  port(A,B,C,D: in BIT; E: out BIT);
end THREE_GATES;
architecture AND_OR of THREE_GATES is
  signal S1,S2: BIT;
  component  OR2
    port(I1,I2: in BIT; O: out BIT);
  end component;
  component  AND2
    port(I1,I2: in BIT; O: out BIT);
  end component;
begin
  C1: AND2
    port map(I1 => A, I2 => B, O => S1);
  C2: AND2
    port map(I1 => C, I2 => D, O => S2);
  C3: OR2
    port map(I1 => S1, I2 => S2, O => E);
end AND_OR;
-- Code continued on the next page.
--Figure 7.59 Delay mapping.

configuration ONE of THREE_GATES is
  for AND_OR
    for all: AND2 use entity work.AND2G(GNR_DEL)
      generic map(DEL => GATE_DEL);
    end for;
    for all: OR2 use entity  work.OR2G(GNR_DEL)
      generic map(DEL => GATE_DEL);
    end for;
  end for;
end ONE;

configuration TWO of THREE_GATES is
  for AND_OR
    for all: AND2 use entity work.AND2G(GNR_DEL)
      generic map(DEL => 2 ns);
    end for;
    for all: OR2 use entity  work.OR2G(GNR_DEL)
      generic map(DEL => 3 ns);
    end for;
  end for;
end TWO;

configuration THREE of THREE_GATES is
  for AND_OR
    for C1: AND2 use entity work.AND2G(GNR_DEL)
      generic map(DEL => 2 ns);
    end for;
    for C2: AND2 use entity work.AND2G(GNR_DEL)
      generic map(DEL => 3 ns);
    end for;
    for C3: OR2 use entity  work.OR2G(GNR_DEL)
      generic map(DEL => 4 ns);
    end for;
  end for;
end THREE;
--Figure 7.60 Delay mapping (continued).