chapter3_models.vhd

James Armstrong VHDL Design , source code

end Z;
---Figure 3.32	Declarative regions.

entity TWO_CONSECUTIVE is
  port(CLK,R,X: in BIT; Z: out BIT);
end TWO_CONSECUTIVE;
use work.all;
architecture STRUCTURAL of TWO_CONSECUTIVE is
  signal Y0,Y1,A0,A1: BIT := '0';
  signal NY0,NX: BIT :='1';
  signal ONE: BIT :='1';
  component EDGE_TRIGGERED_D
    port(CLK,D,NCLR: in BIT;
         Q,QN: out BIT);
  end component;
  for all: EDGE_TRIGGERED_D
    use entity EDGE_TRIG_D(BEHAVIOR); --model pointer
  component INVG
    port(I: in BIT;O: out BIT);
  end component;
  for all: INVG
    use entity INV(BEHAVIOR); --model pointer
  component AND3G
    port(I1,I2,I3: in BIT;O: out BIT);
  end component;
  for all: AND3G
    use entity AND3(BEHAVIOR); --model pointer
  component OR2G
    port(I1,I2: in BIT;O: out BIT);
  end component;
  for all: OR2G
    use entity OR2(BEHAVIOR); --model pointer
begin
  C1: EDGE_TRIGGERED_D
    port map(CLK,X,R,Y0,NY0);
  C2: EDGE_TRIGGERED_D
    port map(CLK,ONE,R,Y1,open);
  C3: INVG
    port map(X,NX);
  C4: AND3G
    port map(X,Y0,Y1,A0);
  C5: AND3G
    port map(NY0,Y1,NX,A1);
  C6: OR2G
    port map(A0,A1,Z);
end STRUCTURAL;
Figure 3.34 Configuration specification for entity TWO_CONSECUTIVE.

configuration PARTS of TWO_CONSECUTIVE is
  for STRUCTURAL
    for all: EDGE_TRIGGERED_D
        use entity work.EDGE_TRIG_D(BEHAVIOR);
    end for;
    for all: INVG
        use entity work.INV(BEHAVIOR);
    end for;
    for all: AND3G
        use entity work.AND3(BEHAVIOR);
    end for;
    for all: OR2G
        use entity work.OR2(BEHAVIOR);
    end for;
  end for;
end PARTS;
--Figure 3.35?Configuration declaration for entity TWO_CONSECUTIVE.

entity TB is 
  end TB;
use WORK.all;
architecture TCTEMPT of TB is
  signal X,R,CLK,Z: BIT;
  component TWIR
    port (CLK,R,X: in BIT;
          Z: out BIT);
  end component;
  for C1: TWIR use configuration work.PARTS;
begin
  C1: TWIR
    port map(CLK,R,X,Z);
  CLK <='0',            '1'after  10 ns,'0'after  20 ns,
        '1'after  30 ns,'0'after  40 ns,'1'after  50 ns,
        '0'after  60 ns,'1'after  70 ns,'0'after  80 ns,
        '1'after  90 ns,'0'after 100 ns,'1'after 110 ns,
        '0'after 120 ns,'1'after 130 ns,'0'after 140 ns;
  X <= '0','1' after  15 ns,'0' after 55 ns;
  R <= '1','0' after 125 ns,'1' after 127 ns;
end TCTEMPT;
--Figure 3.36 Testing the configuration.

entity OBVS is
  generic(N:INTEGER;PER: TIME);
    port(GEN: in BIT);
end OBVS;
use work.all;
architecture FIO of OBVS is
  type INP_COMB is file of BIT_VECTOR;
  file OUTVECT: INP_COMB is out "TEST.VECT";
  signal VECTORS: BIT_VECTOR(N-1 downto 0);
  signal SYNC: BIT;
  component PG
    generic(N: INTEGER; PER: TIME);
    port(START: in BIT;
         PGOUT: out BIT_VECTOR(N-1 downto 0);
         SYNC: inout BIT);
  end component;
  for C1: PG  use entity work.PULSE_GEN(ALG);
begin
  C1: PG
    generic map(N => N, PER => PER)
    port map(START => GEN, PGOUT => VECTORS, SYNC => SYNC);
  WRITE_VECT: process(SYNC)
    variable V: BIT_VECTOR(N-1 downto 0);
  begin
    V := VECTORS;
    WRITE(OUTVECT,V);
  end process WRITE_VECT;
end FIO;
entity IBVS is
  generic(N:INTEGER;PER: TIME);
  port(PLAY: in BIT; BVOUT: out BIT_VECTOR(N-1 downto 0));
end IBVS;
architecture FIO of IBVS is
  type INP_COMB is file of BIT_VECTOR;
  file INVECT: INP_COMB is in "TEST.VECT";
begin
  READ_VECT: process
    variable LENGTH: NATURAL := N;
    variable V: BIT_VECTOR(LENGTH-1 downto 0);
  begin
    wait on PLAY until PLAY = '1';
    loop
      exit when ENDFILE(INVECT);
      READ(INVECT,V,LENGTH);
      BVOUT <= V;
      wait for PER;
    end loop;
  end process READ_VECT;
end FIO;
Figure 3.37 Writing to and reading from a formatted file.

entity TBVS is
  generic(N:INTEGER;PER: TIME);
  port(PLAY: in BIT;
       BVOUT: out BIT_VECTOR(N-1 downto 0));
end TBVS;
use STD.TEXTIO.all;
architecture TIO of TBVS is
begin
  process
    variable VLINE: LINE;
    variable V:BIT_VECTOR(N-1 downto 0);
    file INVECT: TEXT is "TVECT.TEXT";
  begin
    wait on PLAY until PLAY = '1';
    while not(ENDFILE(INVECT)) loop
      READLINE(INVECT,VLINE);
      READ(VLINE,V);
      BVOUT <= V;
      wait for PER;
    end loop;
  end process;
end TIO;
--Figure 3.38 	VHDL code that reads an input file of type TEXT.

package RFP is
  type POWER is range 0 to 1E9
    units pW;
      nw = 1000 pW;
      uW = 1000 nw;
    end units;
  type  FREQUENCY is range 0 to 1E9
    units Hz;
      KHz = 1000 Hz;
      MHz = 1000 KHz;
    end units;
  type RF_SIGNAL is
  record
    STRENGTH: POWER;
    FREQ: FREQUENCY;
  end record;
end RFP;
--Figure 3.39	Package containing declarations for types.

entity TB is
end TB;
use work.RFP.all;
use STD.TEXTIO.all;
architecture TFILE5 of TB is
  signal RFSIG: RF_SIGNAL;
  signal RSIG: BIT;
begin
  process
    variable TEMP_STRENGTH: INTEGER:= 0;
    variable TEMP_FREQ: INTEGER:= 0;
    variable L: LINE;
    file INFILE: TEXT is in "SIGNAL.IN";
  begin
    wait on RSIG until RSIG = '1';
    while not(ENDFILE(INFILE)) loop
      READLINE(INFILE,L);
      READ(L,TEMP_STRENGTH);
      RFSIG.STRENGTH <= TEMP_STRENGTH*1 pW;
      READ(L,TEMP_FREQ);
      RFSIG.FREQ  <= TEMP_FREQ*1 MHz;
      wait for 10 ns;
    end loop;
  end process;
  RSIG <= '1';
end TFILE5;
--Figure 3.40 Reading radar signals with TEXTIO.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DRIVING is
  port(SOUT: out STD_LOGIC);
end DRIVING;
architecture ALG of DRIVING is
  signal INT_SOUT: STD_LOGIC;
begin
  SOUT <= '0','1' after 10 ns,'0' after 20 ns,
          '1' after 30 ns;
  INT_SOUT <= SOUT'DRIVING_VALUE;
end ALG; 
--Figure 3.44 Attribure 'driving_value.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NAND2 is
  generic(DELAY: TIME);
  port(A,B: in STD_LOGIC; C: out STD_LOGIC);
end NAND2;
architecture DF of NAND2 is
begin
  C <= not(A and B) after DELAY;
end DF;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity INVERTER is
  port(I: in STD_LOGIC; O: out STD_LOGIC);
end INVERTER;
architecture STRUCTURE of INVERTER is
begin
  C1: entity work.NAND2(DF)   --- direct instantiation
    generic map(DELAY => 1.0 ns)  -- expressions
    port map(A => I, B => '1',C =>O); --on input ports
end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
configuration NEW_TIMING of INVERTER is
  for STRUCTURE
    for C1: entity work.NAND2(DF)--incremental binding  
      generic map(DELAY => 1.23 ns);
    end for;
  end for;
end NEW_TIMING;
--Figure 3.45 New structural modeling features in VHDL93

entity SHARED_VAR is
  port(START1, START2: in BIT);
end SHARED_VAR;

architecture ALG of SHARED_VAR is
  type PROC_NUM is (PROC1,PROC2);
  shared variable LATEST: PROC_NUM;
begin
  P1: process
  begin
    wait until START1 = '1';
    LATEST := PROC1;
  end process;
  P2: process
  begin
    wait until START2 = '1';
    LATEST := PROC2;
  end process;
end ALG;
--Figure 3.46 Shared Variable

entity IMPURE_F is
end IMPURE_F;

architecture ALG of IMPURE_F is
  signal INT,INT_INC: INTEGER := 0;
  impure function INC_AND_UPDATE
    return INTEGER is 
  begin
    INT <= INT + 1;
    return INT;
  end INC_AND_UPDATE;
begin
  INT_INC <= INC_AND_UPDATE;
end ALG;
--Figure 3.47 Use of an impure function.