chapter5_models.vhd

James Armstrong VHDL Design , source code

   end if;
 end process MEM;
end SIMPLE;
--Figure 5.22 Simple RAM model.

use work.SYSTEM_4.all;
entity ADD_STORE is
  generic(CON_DEL, DO_DEL, MA_DEL, DIS_DEL, CLK_PER: TIME);
  port(RESET,DAV,RACK,WACK: in MVL4;
       MEMEN: out MVL4;
       EN,READ,WRITE: inout MVL4;
       DATA: inout BUS1(7 downto 0):="ZZZZZZZZ";
       DADDR: in MVL4_VECTOR(4 downto 0);
       MADDR: out MVL4_VECTOR(4 downto 0));
end ADD_STORE;
architecture ALG of ADD_STORE is
begin
 CON: process
   variable DATA_REG: MVL4_VECTOR(7 downto 0);
 begin
   if RESET = '1' then
     DATA <= "ZZZZZZZZ"after DIS_DEL; --CS0
   end if;
   wait on DAV until DAV = '1';
------------------------------------------
     EN <= '1' after CON_DEL;      --CS1
   wait for CLK_PER;
------------------------------------------
     EN <= '0' after CON_DEL;
     DATA_REG := SENSE(DATA,'1');  --CS2
   wait for CLK_PER;
------------------------------------------
     MADDR <=  DADDR after MA_DEL;
     MEMEN <= '1' after CON_DEL;   --CS3
     READ <= '1' after CON_DEL;
   wait on RACK until RACK ='1';
------------------------------------------
     DATA_REG := ADD8(SENSE(DATA,'1'),DATA_REG);
     READ <= '0'after CON_DEL;
     MEMEN <= '0'after CON_DEL;    --CS4
   wait for CLK_PER;
------------------------------------------
     DATA <= DRIVE(DATA_REG) after DO_DEL;
     WRITE <= '1'after CON_DEL;
     MEMEN <= '1'after CON_DEL;    --CS5
   wait on WACK until WACK ='1';
------------------------------------------
     WRITE <= '0'after CON_DEL;
     MEMEN <= '0'after CON_DEL;    --CS6
     DATA <= "ZZZZZZZZ" after DIS_DEL;
   wait for CLK_PER;
 end process CON;
end ALG;
--Figure 5.23 Add & Store model.

use work.SYSTEM_4.all;
entity CLOCK_GENERATOR is
  generic(PER: TIME);
  port(RESET: in MVL4; CLK: out MVL4);
end CLOCK_GENERATOR;

architecture IMPL_1 of CLOCK_GENERATOR is
  signal CLOCK: MVL4;
begin
  process (RESET,CLOCK)
    variable CLKE: BIT := '0';
  begin
    if RESET='0' and not RESET'STABLE then
      CLKE := '1';
      CLOCK <= transport '0' after PER/2;
      CLOCK <= transport '1' after PER;
    end if;
    if RESET='1' and not RESET'STABLE then
      CLKE := '0';
    end if;
    if CLOCK='1' and not CLOCK'STABLE and CLKE = '1'then
      CLOCK <= transport '0' after PER/2;
      CLOCK <= transport '1' after PER;
    end if;
      CLK <= CLOCK;
  end process;
end IMPL_1;
--Figure 5.25 Clock generator model.

use work.SYSTEM_4.all;
entity ADU is
  generic(DO_DEL,MA_DEL: TIME);
  port(CS2,CS3,CS4,CS5: MVL4;
       DATA: inout BUS1(7 downto 0) := "ZZZZZZZZ";
       DADDR: in MVL4_VECTOR(4 downto 0);
       MADDR: out MVL4_VECTOR(4 downto 0));
end ADU;
architecture BEHAVIOR of ADU is
begin
 DU: process(CS2,CS3,CS4,CS5)
   variable DATA_REG : MVL4_VECTOR(7 downto 0);
 begin
   if CS2'EVENT or CS4'EVENT then
     if CS2 = '1' then
       DATA_REG:= SENSE(DATA,'1');
     end if;
     if CS4 = '1' then
       DATA_REG:= ADD8(SENSE(DATA,'1'),DATA_REG);
     end if;
   end if;
   if CS3'EVENT and CS3 = '1' then
     MADDR <= DADDR after MA_DEL;
   end if;
   if CS5'EVENT then
     if CS5 = '1' then
       DATA <= DRIVE(DATA_REG) after DO_DEL;
     else
       DATA <= "ZZZZZZZZ";
     end if;
   end if;
 end process DU;
end BEHAVIOR;
--Figure 5.26 ADD unit model.

package INTRES is
  type INTARRAY is array(NATURAL range <>) of INTEGER;
  function INTBUS(S: INTARRAY) return INTEGER;
  subtype RINTEGER is INTBUS INTEGER;
end INTRES;

package body INTRES is
  function INTBUS(S: INTARRAY) return INTEGER is
    begin
      for I in S'RANGE loop
      return S(I);
    end loop;
  end INTBUS;
end INTRES;

use work.INTRES.all;
use work.SYSTEM_4.all;
entity  WAIT_STEPS is
  generic(CLK_DEL,DIS_DEL: TIME);
  port(RUN,X,R: in DOT1 := '0'; S: out RINTEGER);
end WAIT_STEPS;

architecture ONE of WAIT_STEPS is
begin
  process
  begin
    wait until R = '0' and RUN = '1';
LOOP_START: while R = '0'and RUN = '1' loop
       S <= 0;
       next LOOP_START when R = '1';    ---Step 0
    wait until R = '1' for CLK_DEL;
    -----------------------------
       S <= 1;
       next LOOP_START when R = '1';    ---Step 1
    wait until R = '1' for CLK_DEL;
    -----------------------------
       S <= 2;
       next LOOP_START when R = '1';    ---Step 2
    wait until R = '1' for CLK_DEL;
    end loop;
  end process;
end ONE;
--Figure 5.28 Resetting

architecture TWO of WAIT_STEPS is
 signal TRIGGERB,TRIGGERBA,TRIGGERC,TRIGGERCA: DOT1 := '0';
 signal SINT: RINTEGER register;
begin
A: process
  begin
    SINT <= null;
   wait on RUN,TRIGGERBA,TRIGGERCA until RUN = '1';
    SINT <= 0;                          ---Step 0
   wait for CLK_DEL;
    SINT <= 1;                          ---Step 1
   wait for CLK_DEL;
    SINT <= null;
    if X = '1' then
      TRIGGERB <= not(TRIGGERB);
    else
      TRIGGERC <= not(TRIGGERC);
    end if;
  end process A;
B: process
  begin
    SINT <= null;
   wait on TRIGGERB;
    SINT <= 2;                          ---Step 2
   wait for CLK_DEL;
    SINT <= 3;                          ---Step 3
   wait for CLK_DEL;
    SINT <= null;
    TRIGGERBA <= not(TRIGGERBA);
  end process B;
C: process
  begin
    SINT <= null;
   wait on TRIGGERC;
    SINT <= 4;                          ---Step 4
   wait for CLK_DEL;
    SINT <= 5;                          ---Step 5
   wait for CLK_DEL;
    SINT <= null;
    TRIGGERCA <= not(TRIGGERCA);
  end process C;
  S <= SINT;
end TWO;
--Figure 5.29 Branching

use work.SYSTEM_4.all;
entity TIME_MUX is
  generic(DEL1,DEL2: TIME);
  port(PHASE_ONE,PHASE_TWO: in MVL4;
       Z: out DOTX := '0');
end TIME_MUX;
architecture  GUARDED_BLOCK0 of TIME_MUX is
begin
  PH_ONE: block(PHASE_ONE = '1')
  begin
    Z <= guarded '0' after DEL1;
  end block PH_ONE;
  PH_TWO: block(PHASE_TWO = '1')
  begin
    Z <= guarded '1' after DEL2;
  end block PH_TWO;
end GUARDED_BLOCK0;
--Figure 5.30 Time multiplexing with two guarded blocks

architecture  GUARDED_BLOCK1 of TIME_MUX is
  signal ZINT: DOTX register;
begin
  PH_ONE: block(PHASE_ONE = '1')
  begin
    ZINT <= guarded '0' after DEL1;
  end block PH_ONE;
  PH_TWO: block(PHASE_TWO = '1')
  begin
    ZINT <= guarded '1' after DEL2;
  end block PH_TWO;
  Z <= ZINT;
end GUARDED_BLOCK1;
--Figure 5.32 ZINT as a register.

architecture  GUARDED_BLOCK2 of TIME_MUX is
  signal ZINT: DOTX bus;
begin
  PH_ONE: block(PHASE_ONE = '1')
  begin
    ZINT <= guarded '0' after DEL1;
  end block PH_ONE;
  PH_TWO: block(PHASE_TWO = '1')
  begin
    ZINT <= guarded '1' after DEL2;
  end block PH_TWO;
  Z <= ZINT;
end GUARDED_BLOCK2;
---Figure 5.33 ZINT as a bus.

architecture PROC of TIME_MUX is
begin
  PH_ONE: process(PHASE_ONE)
  begin
    if PHASE_ONE = '1' then
      Z <= '0' after DEL1;
    end if;
  end process PH_ONE;
  PH_TWO: process(PHASE_TWO)
  begin
    if PHASE_TWO = '1' then
      Z <= '1' after DEL2;
    end if;
  end process PH_TWO;
end PROC;
--Figure 5.35 Two processes driving Z.

architecture PROC_NULL of TIME_MUX is
  signal ZINT: DOTX register;
begin
  PH_ONE: process(PHASE_ONE)
  begin
    if PHASE_ONE = '1' then
      ZINT <= '0' after DEL1;
    else
      ZINT <= null;
    end if;
  end process PH_ONE;
  PH_TWO: process(PHASE_TWO)
  begin
    if PHASE_TWO = '1' then
      ZINT <= '1' after DEL2;
    else
      ZINT <= null;
    end if;
  end process PH_TWO;
  Z <= ZINT;
end PROC_NULL;
--Figure 5.36 Solution for two processes driving a single signal.

entity TIME_MUX is
  generic(DEL1,DEL2: TIME);
  port(PHASE_ONE,PHASE_TWO: in MVL4;
       Z: buffer MVL4);
end TIME_MUX;

architecture QUIET_MUX of TIME_MUX is
  signal  PH1,PH2,Z1,Z2: MVL4;
begin
  PH_ONE: process(PHASE_ONE)
  begin
    if PHASE_ONE = '1' then
      Z1 <= '0' after DEL1;
    end if;
  end process PH_ONE;
  PH_TWO: process(PHASE_TWO)
  begin
    if PHASE_TWO = '1' then
      Z2 <= '1' after DEL2;
    end if;
  end process PH_TWO;
  Z <= Z1 when not Z1'quiet else
       Z2 when not Z2'quiet else
       Z;
end QUIET_MUX;
Figure 5.37'Quiet multiplexer.