📄 chapter8_models.vhd
字号:
-- Shift in the fourth bit
SHIFT_REG <= D & SHIFT_REG(3 downto 1);
-- Control Section
if R='0' then
STATE <= S5;
elsif R='1' then
STATE <= S0;
end if;
when S5 =>
-- Data Section
-- Control Section
if R='0' and A='1' then
STATE <= S1;
elsif R='1' or A='0' then
STATE <= S0;
end if;
end case;
end if;
end process STATE;
--
-- Output process
--
OUTPUT: process (STATE)
begin
case STATE is
when S0 to S4 =>
DONE <= '0';
when S5 =>
DONE <= '1';
Z <= SHIFT_REG;
end case;
end process OUTPUT;
end FSM_RTL;
--Figure 8.25b VHDL model for serial to parallel converter (cont
entity TWO_CONSECUTIVE is
port(CLK,R,X: in BIT; Z: out BIT);
end TWO_CONSECUTIVE;
--
architecture FSM of TWO_CONSECUTIVE is
type STATE is (S0,S1,S2);
signal FSM_STATE: STATE := S0;
type TRANSITION is record
OUTPUT: BIT;
NEXT_STATE: STATE;
end record;
type TRANSITION_MATRIX is array(STATE,BIT) of TRANSITION;
constant STATE_TRANS: TRANSITION_MATRIX :=
(S0 => ('0' => ('0',S1), '1' => ('0',S2)),
S1 => ('0' => ('1',S1), '1' => ('0',S2)),
S2 => ('0' => ('0',S1), '1' => ('1',S2)));
begin
process(R,X,CLK,FSM_STATE)
begin
if R = '0' then -- Reset
FSM_STATE <= S0;
elsif CLK'EVENT and CLK ='1' then -- Clock event
FSM_STATE <= STATE_TRANS(FSM_STATE,X).NEXT_STATE;
end if;
if FSM_STATE'EVENT or X'EVENT then -- Output Function
Z <= STATE_TRANS(FSM_STATE,X).OUTPUT;
end if;
end process;
end FSM;
--Figure 8.26 Algorithmic model of a state table using records and aggregates.
-- Basic MicroCoded Control Unit
entity BMCU is
generic (AGL_DELAY, MAR_DELAY, ROM_DELAY, MIR_DELAY: TIME);
port (C: in BIT_VECTOR (23 downto 0)--Cond. from data unit.
:=B"0000_0000_0000_0000_0000_0000";
CLK,RESET: in BIT:='0'; -- System clock and reset.
LCS: out BIT_VECTOR (31 downto 0));--Level Control
end BMCU; --Signals to data unit.
--
-- Algorithmic level VHDL description of BMCU.
use work.BMCU_FUNCTIONS.all;
architecture ALGORITHMIC of BMCU is
-- MAR is the Memory Address Register for the ROM.
-- MIR is the Memory Instruction Register for the ROM.
signal MAR,NMAR: BIT_VECTOR (7 downto 0);-- NMAR is nxt val
signal CWORD: BIT_VECTOR (63 downto 0);-- Control word
signal MIR: BIT_VECTOR (63 downto 0);
signal NAD: BIT_VECTOR (7 downto 0);-- Branch address
signal CS: BIT_VECTOR (23 downto 0);-- Condition Select
begin
-- Memory Address Register process.
MARP: process (CLK, RESET)
begin
if RESET='1' then
MAR <= B"0000_0000" after MAR_DELAY;
elsif CLK'event and CLK='0' then
MAR <= NMAR after MAR_DELAY;
end if;
end process MARP;
-- Memory Instruction Register Process
MIRP: process (CLK, RESET)
begin
if RESET='1' then MIR <=
B"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
after MIR_DELAY;
elsif CLK'event and CLK='1' then
MIR <= CWORD after MIR_DELAY;
end if;
end process MIRP;
-- Model code continued in next figure.
--Figure 8.38a An algorithmic level VHDL description for BMCU.
-- ROM process
ROMP: process (MAR)
type MEM_TYPE is array (0 to 255
of BIT_VECTOR (63 downto 0);
constant MEM: MEM_TYPE:=
--|<-------- CS --------->|<-NAD->|<------------- LCS ----------->|
(0=>B"0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000",
1=>B"0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000",
2=>B"0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000",
others => (others => '0'));
begin
CWORD <= MEM(BIT_VECTOR_TO_INT(MAR)) after ROM_DELAY;
end process ROMP;
-- Decode the MIR to obtain NAD,CS, and LCS.
DECODEP: process (MIR)
begin
NAD <= MIR(39 downto 32);
LCS <= MIR(31 downto 0);
CS <= MIR(63 downto 40);
end process DECODEP;
-- Address generation process.
AGL: process (MAR, NAD, C, CS)
variable AS: BIT; -- AS is TRUE if selected condition is TRUE.
begin
AS:=(CS(23) and C(23)) or (CS(22) and C(22)) or (CS(21) and C(21))
or (CS(20) and C(20)) or (CS(19) and C(19)) or (CS(18) and C(18))
or (CS(17) and C(17)) or (CS(16) and C(16)) or (CS(15) and C(15))
or (CS(14) and C(14)) or (CS(13) and C(13)) or (CS(12) and C(12))
or (CS(11) and C(11)) or (CS(10) and C(10)) or (CS(9) and C(9))
or (CS(8) and C(8)) or (CS(7) and C(7)) or (CS(6) and C(6))
or (CS(5) and C(5)) or (CS(4) and C(4)) or (CS(3) and C(3))
or (CS(2) and C(2)) or (CS(1) and C(1)) or (CS(0) and C(0));
case AS is
when '0' => NMAR <= INC(MAR) after AGL_DELAY;
when '1' => NMAR <= NAD after AGL_DELAY;
end case;
end process AGL;
end ALGORITHMIC;
--Figure 8.38b An algorithmic level VHDL description for BMCU (cont.).
-- Package of functions for BMCU.
--
package BMCU_FUNCTIONS is
function BIT_VECTOR_TO_INT(VEC: BIT_VECTOR) return INTEGER;
function INC(A: BIT_VECTOR) return BIT_VECTOR;
end BMCU_FUNCTIONS;
--
package body BMCU_FUNCTIONS is
-- Convert a BIT_VECTOR to INTEGER.
function BIT_VECTOR_TO_INT(VEC: BIT_VECTOR)return INTEGER is
variable SUM, WT: INTEGER:=0;
begin
if VEC'right <= VEC'left then
for N in VEC'right to VEC'left loop
if VEC(N)='1' then
SUM := SUM + (2 ** WT);
end if;
WT := WT+1;
end loop;
else
for N in VEC'right downto VEC'left loop
if VEC(N)='1' then
SUM := SUM + (2 ** WT);
end if;
WT := WT+1;
end loop;
end if;
return SUM;
end BIT_VECTOR_TO_INT;
--Figure 8.39a Package of functions for BMCU algorithmic level model.
-- Increment a BIT_VECTOR.
function INC(A: BIT_VECTOR) return BIT_VECTOR is
variable CARRY: BIT:='1';
variable RESULT: BIT_VECTOR (A'range);
begin
if A'right <= A'left then
for N in A'right to A'left loop
if CARRY = '1' then
RESULT(N) := not A(N);
else
RESULT(N) := A(N);
end if;
CARRY := CARRY and A(N);
end loop;
else
for N in A'right downto A'left loop
if CARRY = '1' then
RESULT(N) := not A(N);
else
RESULT(N) := A(N);
end if;
CARRY := CARRY and A(N);
end loop;
end if;
return RESULT;
end INC;
end BMCU_FUNCTIONS;
--Figure 8.39b Package of functions for BMCU algorithmic level model (cont.).
-- Algorithmic level VHDL description of BMCU.
use work.BMCU_FUNCTIONS.all;
architecture STOP of BMCU is
-- MAR is the Memory Address Register for the ROM.
-- MIR is the Memory Instruction Register for the ROM.
signal MAR, NMAR: BIT_VECTOR (7 downto 0);-- NMAR is next value.
signal CWORD: BIT_VECTOR (63 downto 0);-- Control word from ROM.
signal MIR: BIT_VECTOR (63 downto 0);--Word read from ROM.
signal NAD: BIT_VECTOR (7 downto 0); -- Branch address.
signal CS: BIT_VECTOR (23 downto 0); -- Condition Select Field
begin
-- Memory Address Register process.
MARP: process (CLK, RESET)
begin
if RESET='1' then
MAR <= B"0000_0000" after MAR_DELAY;
elsif CLK'event and CLK='0' then
MAR <= NMAR after MAR_DELAY;
end if;
end process MARP;
-- Memory Instruction Register Process
MIRP: process (CLK, RESET)
begin
if RESET='1' then MIR <=
B"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
after MIR_DELAY;
elsif CLK'event and CLK='1' then
MIR <= CWORD after MIR_DELAY;
end if;
end process MIRP;
-- ROM process
ROMP: process (MAR)
type MEM_TYPE is array (0 to 255) of BIT_VECTOR (63 downto 0);
constant MEM: MEM_TYPE:=
-----|<------- CS ------->|<-NAD->|<---------- LCS ---------->|
(0=>B"01000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000",
1=>B"10000000_00000000_00000000_00000000_10000000_00000000_00000000_00000000",
2=>B"10000000_00000000_00000000_00000000_10000000_00000000_00000000_00000000",
3=>B"10000000_00000000_00000000_00000000_10000000_00000000_00000000_00000000",
4=>B"10000000_00000000_00000000_00000000_10000000_00000000_00000000_00000000",
5=>B"00100000_00000000_00000000_00000001_01000000_00000000_00000000_00000000",
6=>B"01000000_00000000_00000000_00000000_01000000_00000000_0000_000_00000000",
others => (others => '0'));
begin
CWORD <= MEM(BIT_VECTOR_TO_INT(MAR)) after ROM_DELAY;
end process ROMP;
-- Code is continued on next page.
--Figure 8.47a VHDL model for STOP control unit.
-- Decode the MIR to obtain NAD and S.
DECODEP: process (MIR)
begin
NAD <= MIR(39 downto 32);
LCS <= MIR(31 downto 0);
CS <= MIR(63 downto 40);
end process DECODEP;
-- Address generation process.
AGL: process (MAR, NAD, C, CS)
variable AS: BIT; -- Selected condition is TRUE.
begin
AS := (CS(23) and C(23)) or (CS(22) and C(22)) or
(CS(21) and C(21)) or (CS(20) and C(20)) or
(CS(19) and C(19)) or (CS(18) and C(18)) or
(CS(17) and C(17)) or (CS(16) and C(16)) or
(CS(15) and C(15)) or (CS(14) and C(14)) or
(CS(13) and C(13)) or (CS(12) and C(12)) or
(CS(11) and C(11)) or (CS(10) and C(10)) or
(CS( 9) and C( 9)) or (CS( 8) and C( 8)) or
(CS( 7) and C( 7)) or (CS( 6) and C( 6)) or
(CS( 5) and C( 5)) or (CS( 4) and C( 4)) or
(CS( 3) and C( 3)) or (CS( 2) and C( 2)) or
(CS( 1) and C( 1)) or (CS( 0) and C( 0));
case AS is
when '0' => NMAR <= INC(MAR) after AGL_DELAY;
when '1' => NMAR <= NAD after AGL_DELAY;
end case;
end process AGL;
end STOP;
--Figure 8.47b VHDL model for STOP control unit (cont.).
-- Data Unit for Serial to Parallel Converter
--
entity DATASTOP is
generic (SHIFT_DELAY, GATE_DELAY: TIME);
port (R, A, D, CLK, SHIFT, DONE_CONTROL: in BIT;
Z: out BIT_VECTOR(3 downto 0);
DONE, C23, C22, C21: out BIT);
end DATASTOP;
--
architecture DATAFLOW of DATASTOP is
signal SHIFT_REG: BIT_VECTOR (3 downto 0);
begin
--
-- Shift register
--
SHIFT_REG <= D & SHIFT_REG(3 downto 1) after SHIFT_DELAY
when CLK'event and CLK='1' and SHIFT='1'
else SHIFT_REG;
--
-- Condition signals needed in the control unit.
--
C23 <= R;
C22 <= R or not A after GATE_DELAY;
C21 <= not R and A after GATE_DELAY;
--
-- Output signals
--
DONE <= DONE_CONTROL;
Z <= SHIFT_REG;
end DATAFLOW;
--Figure 8.48 VHDL model for STOP data unit.
use work.all;
entity TEST_BENCH is
end TEST_BENCH;
--
architecture BMCU_TEST of TEST_BENCH is
signal R,A,D,CLK,INIT,RESET: BIT;
signal C23, C22, C21: BIT;
signal SHIFT, DONE_CONTROL: BIT;
signal DONE: BIT;
signal Z: BIT_VECTOR (3 downto 0);
signal X: BIT_VECTOR (3 downto 1);
signal F: BIT; -- Constant false signal.
--
component DATA_UNIT
generic (SHIFT_DELAY, GATE_DELAY: TIME);
port (R, A, D, CLK, SHIFT, DONE_CONTROL: in BIT;
Z: out BIT_VECTOR(3 downto 0);
DONE, C23, C22, C21: out BIT);
end component;
--
component MICRO_CONTROL_UNIT
generic (AGL_DELAY, MAR_DELAY, ROM_DELAY, MIR_DELAY,
MIR_SETUP, MAR_SETUP: TIME);
port (C: in BIT_VECTOR (23 downto 0); -- Conditions.
CLK, RESET: in BIT; -- System clock and reset.
LCS: out BIT_VECTOR (31 downto 0));-- Level CS.
end component;
--
-- Component configuration statememts.
for L1: DATA_UNIT use entity DATASTOP(DATAFLOW);
for L2: MICRO_CONTROL_UNIT use entity BMCU(STOP);
begin
L1: DATA_UNIT
generic map (20 ns, 10 ns)
port map (R, A, D, CLK, SHIFT, DONE_CONTROL, Z,
DONE, C23, C22, C21);
L2: MICRO_CONTROL_UNIT
generic map (50 ns, 20 ns, 50 ns, 20 ns, 5 ns, 5 ns)
port map (C(23) => C23, C(22) => C22, C(21) => C21,
C( 0) => F, C( 1) => F, C( 2) => F, C( 3) => F,
C( 4) => F, C( 5) => F, C( 6) => F, C( 7) => F,
C( 8) => F, C( 9) => F, C(10) => F, C(11) => F,
C(12) => F, C(13) => F, C(14) => F, C(15) => F,
C(16) => F, C(17) => F, C(18) => F, C(19) => F,
C(20) => F,
RESET => RESET, CLK => CLK,
LCS(31) => SHIFT, LCS(30) => DONE_CONTROL);
-- Code continued on next page.
--Figure 8.49a Test bench for STOP system.
-- Clock process
process
begin
CLK <= '0';
wait for 200 ns;
CLK <= '1';
wait for 200 ns;
end process;
--
-- Process to provide inputs.
F <= '0';
RESET <= '1', '0' after 30 ns;
process (X)
begin
R <= X(3);
A <= X(2);
D <= X(1);
end process;
--
-- Assignment of values to input X
X <= "100" after 50 ns, "010" after 650 ns,
"001" after 1050 ns, "000" after 1450 ns,
"001" after 1850 ns, "001" after 2250 ns,
"000" after 2650 ns, "000" after 3050 ns,
"010" after 3450 ns, "000" after 3850 ns,
"001" after 4250 ns, "001" after 4650 ns,
"000" after 5050 ns, "010" after 5450 ns,
"001" after 5850 ns, "001" after 6250 ns,
"011" after 6650 ns, "010" after 7050 ns,
"010" after 7450 ns, "000" after 7850 ns,
"101" after 8250 ns, "001" after 8650 ns,
"001" after 9050 ns, "000" after 9450 ns,
"001" after 9850 ns, "000" after 10250 ns,
"001" after 10650 ns, "000" after 11050 ns,
"000" after 11450 ns;
end BMCU_TEST;
--Figure 8.49b Test bench for STOP system (cont.).
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -