chapter4_models.vhd

James Armstrong VHDL Design , source code

   type OR_ARRAY is array(1 to 4,1 to 4) of BIT;
   variable OR_PLANE: OR_ARRAY :=
     (('1','0','0','0'),('1','0','1','0'),
      ('0','1','0','0'),('0','0','1','1'));
 begin
   for I in 1 to 4 loop
     ZV(I) := '0';
     for J in 1 to 4 loop
       if OR_PLANE(I,J) = '1' then ZV(I) := ZV(I) or R(J);
       end if;
     end loop;
     Z(I) <= ZV(I) after OR_DEL;
   end loop;
 end process OR_PLANE;
end CONNECTION_MATRIX;
--Figure 4.30 PLA model.

entity JKFF is
  generic(SRDEL,CLKDEL: TIME);
  port(S,R,J,K,CLK: in BIT; Q,QN: inout BIT);
end JKFF;

architecture ALG of JKFF is
begin
  process(CLK,S,R)
  begin
    if S = '1' and R = '0' then
      Q <= '1' after SRDEL;
      QN <= '0' after SRDEL;
    elsif S = '0' and R = '1' then
      Q  <= '0' after SRDEL;
      QN <= '1' after SRDEL;
    elsif CLK'EVENT and CLK = '1' and S='0' and R='0' then
      if J = '1' and K = '0' then
        Q <= '1' after CLKDEL;
        QN <= '0' after CLKDEL;
      elsif J = '0' and K ='1'  then
        Q <= '0' after CLKDEL;
        QN <= '1' after CLKDEL;
      elsif J= '1' and K= '1'  then
        Q <= not Q after CLKDEL;
        QN <= not QN after CLKDEL;
      end if;
    end if;
  end process;
end ALG;
--Figure 4.31 JK flip-flop model.

entity REG is
  generic(DEL: TIME);
  port(RESET,LOAD,CLK: in BIT;
       DATA_IN: in BIT_VECTOR(3 downto 0);
       Q: inout BIT_VECTOR(3 downto 0));
end REG;

architecture DF of REG is
begin
  REG: block(not CLK'STABLE and CLK ='1')
  begin
    Q <= guarded "0000" after DEL when RESET ='1' else
         DATA_IN after DEL when LOAD ='1' else
         Q;
  end block REG;
end DF;
--Figure 4.32 Register model.

entity LATCH is
  generic(LATCH_DEL:TIME);
  port(D: in BIT_VECTOR(7 downto 0);
       CLK: in BIT; LOUT: out BIT_VECTOR(7 downto 0));
end LATCH;

architecture DFLOW of LATCH is
begin
  LATCH: block(CLK = '1')
  begin
    LOUT <= guarded D after LATCH_DEL;
  end block LATCH;
end DFLOW;
--Figure 4.33 Latch primitive.

entity SHIFTREG is
  generic(DEL: TIME);
  port(DATA_IN: in BIT_VECTOR(3 downto 0);
       CLK,LOAD,SR,SL: in BIT; IL,IR: in BIT;
       Q: inout BIT_VECTOR(3 downto 0));
end SHIFTREG;

architecture  DF of SHIFTREG is
begin
  SH:block(not CLK'STABLE and CLK ='1')
  begin
    Q <= guarded DATA_IN after DEL when LOAD= '1' else
    Q(2 downto 0) & IL after DEL when SL='1' and SR='0' else
    IR & Q(3 downto 1) after DEL when SL='0' and SR='1' else
    Q;
  end block SH;
end DF;
--Figure 4.35 Shift register primitive.

entity COUNTER is
  generic(DEL:TIME);
  port(RESET,LOAD,COUNT,UP,CLK: in BIT;
       DATA_IN: in BIT_VECTOR(3 downto 0);
       CNT: inout BIT_VECTOR(3 downto 0));
end COUNTER;
use work.PRIMS.all;
architecture ALG of COUNTER is
begin
  process(CLK)
  begin
    if CLK = '1' then
      if RESET = '1' then
        CNT <= "0000" after DEL;
      elsif LOAD ='1' then
        CNT <= DATA_IN after DEL;
      elsif COUNT ='1' then
        if UP = '1' then
          CNT <= INC(CNT) after DEL;
        else
          CNT <= DEC(CNT) after DEL;
        end if;
      end if;
    end if;
  end process;
end ALG;
--Figure 4.36 Counter primitive.

use work.PRIMS.all;
entity RAM is
  generic (RDEL,DISDEL: TIME);
  port (DATA: inout BIT_VECTOR(3 downto 0);
        ADDRESS: in BIT_VECTOR(4 downto 0);
        RD,WR,NCS: in BIT);
end RAM;

architecture SIMPLE of RAM is
  type MEMORY is array(0 to 31) of BIT_VECTOR(3 downto 0);
begin
  process(RD,WR,NCS,ADDRESS,DATA)
    variable MEM: MEMORY;
  begin
    if NCS='0' then
      if RD='1' then
        DATA <= MEM(INTVAL(ADDRESS)) after RDEL;
      elsif WR='1'then
        MEM(INTVAL(ADDRESS)) := DATA;
      end if;
    else
      DATA <= "1111" after DISDEL;
    end if;
  end process;
end SIMPLE;
--Figure 4.37 RAM primitive.

entity CLOCK_GENERATOR
  generic(PER: TIME);
  port(RUN: in BIT; CLK: out BIT);
end CLOCK_GENERATOR;

architecture ALG of CLOCK_GENERATOR is
  signal CLOCK: BIT;
begin
  process (RUN,CLOCK)
    variable CLKE: BIT := '0';
  begin
    if RUN='1' and not RUN'STABLE then
      CLKE := '1';
      CLOCK <= transport '0' after PER/2;
      CLOCK <= transport '1' after PER;
    end if;
    if RUN='0' and not RUN'STABLE then
      CLKE := '0';
    end if;
    if CLOCK='1' and not CLOCK'STABLE  and CLKE = '1'then
      CLOCK <= transport '0' after PER/2;
      CLOCK <= transport '1' after PER;
    end if;
    CLK <= CLOCK;
  end process;
end ALG;
--Figure 4.38 Feedback oscillator.

entity COSC is
  generic(HI_TIME,LO_TIME: TIME);
  port(RUN: in BIT; CLOCK: out BIT := '0');
end COSC;
architecture ALG of COSC is
begin
  process
  begin
    wait until RUN ='1';
    while RUN = '1'  loop
      CLOCK <= '1';
      wait for HI_TIME;
      CLOCK <= '0';
      wait for LO_TIME;
    end loop;
  end process;
end ALG;
--Figure 4.39 WAIT statement oscillator.

entity TEST_BENCH
is end TEST_BENCH;

use STD.TEXTIO.all;
use WORK.all;
architecture ONES_CNT1 of TEST_BENCH is
  signal PLAY: BIT;
  signal A: BIT_VECTOR(2 downto 0);
  signal C: BIT_VECTOR(1 downto 0);
  component ONES_CNTA
    port (PLAY: in BIT; A: in BIT_VECTOR(2 downto 0);
          C: out BIT_VECTOR(1 downto 0));
  end component;
  for L1: ONES_CNTA use entity ONES_CNT(ALGORITHMIC);
begin
  L1: ONES_CNTA
    port map(PLAY, A, C);
  process
    variable VLINE: LINE;
    variable V1: BIT_VECTOR(2 downto 0);
    variable V2: BIT_VECTOR(1 downto 0);
    file INVECT: TEXT is "TVECT.TEXT";
  begin
    PLAY<= '0', '1' after 3 ns;
    wait on PLAY until PLAY = '1';
    while not(ENDFILE(INVECT)) loop
      READLINE(INVECT, VLINE);
      READ(VLINE, V1);
      READ(VLINE, V2);
      A<= V1;
      wait for 1 ns;
      assert (V2 = C)
        report "WARNING: C is NOT equal to (V2 or C)"
          severity WARNING;
    end loop;
  end process;
end ONES_CNT1;
--Figure 4.41 Text I/O Test Bench

S <= '1' after 10 ns, '0' after 220 ns, '1' after 920 ns,
     '0' after 1120 ns;
R <= '1' after 230 ns, '0' after 420 ns, '1' after 1320 ns,
     '0'after 1420 ns;
J <= '1' after 500 ns, '0' after 600 ns, '1' after 700 ns;
K <= '1' after 600 ns;
CLK <='1' after 50 ns,  '0' after 100 ns, '1' after 150 ns,
      '0' after 200 ns, '1' after 250 ns, '0' after 300 ns,
      '1' after 350 ns, '0' after 400 ns, '1' after 450 ns,
      '0' after 500 ns, '1' after 550 ns, '0' after 600 ns,
      '1' after 650 ns, '0' after 700 ns, '1' after 750 ns,
      '0' after 800 ns, '1' after 850 ns, '0' after 900 ns,
      '1' after 950 ns, '0' after 1000 ns,'1' after 1050 ns,
      '0' after 1100 ns,'1' after 1150 ns,'0' after 1200 ns,
      '1' after 1250 ns,'0' after 1300 ns,'1' after 1350 ns,
      '0' after 1400 ns,'1' after 1450 ns,'0' after 1500 ns,
      '1' after 1550 ns,'0' after 1600 ns,'1' after 1650 ns,
      '0' after 1700 ns;
-- Figure 4.42 Generating test vectors for a JK flip-flop using signal assignment
 --statements

entity PULSE_GEN is
  generic(N: INTEGER; PER: TIME);
  port(START: in BIT; PGOUT: out BIT_VECTOR(N-1 downto 0));
end PULSE_GEN;
architecture ALG of PULSE_GEN is
  function INT_TO_BIN (INPUT : INTEGER;N : POSITIVE)
    return BIT_VECTOR is
    variable FOUT: BIT_VECTOR(0 to N-1);
    variable TEMP_A: INTEGER:= 0;
    variable TEMP_B: INTEGER:= 0;
  begin   -- Beginning of function body.
    TEMP_A := INPUT;
    for I in N-1 downto 0 loop
      TEMP_B := TEMP_A/(2**I);
      TEMP_A := TEMP_A rem (2**I);
      if (TEMP_B = 1) then
        FOUT(N-1-I) := '1'; else
        FOUT(N-1-I) := '0';
      end if;
    end loop;
    return FOUT;
  end INT_TO_BIN;
begin    -- Beginning of architecture body.
  process(START)
  begin
    for I in 0 to 2**N-1 loop
      PGOUT <= transport INT_TO_BIN(I,N) after I*PER;
    end loop;
  end process;
end ALG;
--Figure 4.43 Input combination generator.

entity TEST_BENCH is 
end TEST_BENCH;

use work.all;
architecture JKFF_TEST of TEST_BENCH is
  signal RUN, CLOCK, START, S, R, J, K, CLK, Q, QN: in BIT;
  signal PGOUT: BIT_VECTOR(3 downto 0);
------------ OSCILLATOR--------------------------
  component OSCILLATOR
    generic(HI_TIME, LO_TIME: TIME);
    port(RUN: in BIT; CLOCK: out BIT:= '0');
  end component;
------------ INPUT COMBINATION GENERATOR --------
  component ICG
    generic(N: INTEGER; PER: TIME);
    port(START: IN BIT; PGOUT: out BIT_VECTOR(N-1 downto 0));
  end component;
------------ JKFF -------------------------------
  component JK
    generic(SRDEL, CLKDEL: TIME);
    port(S, R, J, K: in BIT; CLK: in BIT; Q, QN: inout BIT);
  end component;
  for T1: OSCILLATOR use entity COSC(ALG);
  for T2: ICG use entity PULSE_GEN(ALG);
  for T3: JK use entity JKFF(ALG);
  signal PG: BIT_VECTOR(3 downto 0);
  signal OSC: BIT;
begin
  T1: OSCILLATOR
    generic map(25 ns, 25 ns)
    port map(RUN, OSC);
  T2: ICG
    generic map(4, 50 ns)
    port map(START, PG);
  T3: JK
    generic map( 12 ns, 15 ns)
    port map(PG(3), PG(0), PG(2), PG(1), OSC, Q, QN);
  process
  begin
    RUN<='0', '1' after 50 ns, '0' after 9000 ns; 
    START<= '1', '0' after 25 ns;
    wait;
  end process;
end JKFF_TEST;
--Figure 4.44?Testbench using input generator primitives.