exp3-04.v

来自「verilog大量源程序」· Verilog 代码 · 共 12 行

/*	4-1 SELECTOR	*/
module	SEL	( A, B, C, D, SEL, F );
   input	A, B, C, D;
   input	[1:0] SEL;
   output	F;

   assign	F= ~SEL[1] & ~SEL[0] & A
			         | ~SEL[1] &  SEL[0] & B
			         |  SEL[1] & ~SEL[0] & C
			         |  SEL[1] &  SEL[0] & D;
endmodule