exp3-14.tst

verilog大量源程序

/*	4-1 SELECTOR_TEST	*/
`timescale	1ns/1ns
module	SEL_TEST;
   reg	[3:0] IN;
   reg	[1:0] SEL_IN;
   wire	F;

	SEL	SEL	( IN[0], IN[1], IN[2], IN[3], SEL_IN, F );
	always	#150	SEL_IN = SEL_IN + 1;
	always	 #50	IN = IN + 1;
	initial	begin
	   IN = 0; SEL_IN = 0;
		 #1200	$finish;
	end
endmodule