exp3-22.tst

verilog大量源程序

`timescale 1ns/1ns

/* ENCORDER_TEST	*/
module ENC_TEST;
    reg	       [3:0]	IN;
    wire       [1:0]	Y;
    integer	i,j;

    ENC	ENC	( IN, Y );

    initial	begin

	    j = {2'b10, 2'b0, 1'b1};

            for ( i = 0; i <= 3; i = i + 1 )
			begin
			   j=j>>1;
			   IN = j[3:0];
			   #200;
			end
		$finish;
	end
endmodule