exp3-09.v

来自「verilog大量源程序」· Verilog 代码 · 共 17 行

/*   2-1 SELECTOR   */
module	SEL	( A, B, SEL, F );
   input	A, B, SEL;
   output	F;

   assign	F= SEL2_1_FUNC ( A, B, SEL );

   function	SEL2_1_FUNC;
      input	A, B, SEL;
	    
      case ( SEL )
		    0:SEL2_1_FUNC = A;
		    1:SEL2_1_FUNC = B;
	    endcase
   endfunction
endmodule