exp3-06.v

来自「verilog大量源程序」· Verilog 代码 · 共 11 行

/*	4-1 SELECTOR	*/
module	SEL	( A, B, C, D, SEL, F );
   input	A, B, C, D;
   input	[1:0] SEL;
   output	F;

	 assign	F = ( SEL[1] == 0 )?
		              (( SEL[0] == 0 )? A: B ):(( SEL[0] == 0 )? C: D );
endmodule