exp3-08.v

来自「verilog大量源程序」· Verilog 代码 · 共 25 行

/*	4-1 SELECTOR	*/
module	SEL	( A, B, C, D, SEL, F );
   input	A, B, C, D;
   input	[1:0] SEL;
   output	F;

   assign	F= SEL4_1_FUNC ( A, B, C, D, SEL );

   function	SEL4_1_FUNC;
      input	A, B, C, D;
      input	[1:0] SEL;
      
      if ( SEL[1] == 0 )
		    if ( SEL[0] == 0 )
			     SEL4_1_FUNC = A;
		    else
			     SEL4_1_FUNC = B;
	    else
         if ( SEL[0] == 0 )
			     SEL4_1_FUNC = C;
		    else
			     SEL4_1_FUNC = D;
   endfunction
endmodule